Vertical Channel Memory Structure With Bonded Power Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face challenges in increasing integration, operating speed, and yield, particularly with the reduction in design rules, where transistors with vertical channels are needed to enhance these characteristics.
Innovation Solution
A semiconductor memory device design incorporating a lower and upper structure with specific electrical connections, including bonding pads and backside through vias, to improve integration and reduce resistance, utilizing vertical channel transistors and advanced wiring layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistors are used, then manufacturing is simpler, but integration density and current driving capability are limited
Solution Approach 1:
The patent transitions from planar (2D) transistors to vertical channel (3D) transistors, utilizing the third dimension to increase integration density. The vertical channel structure allows multiple transistors to be stacked within a smaller footprint area, thereby improving productivity without proportionally increasing device complexity.
Solution Approach 2:
The patent implements stacked transistor structures where multiple active regions are vertically nested within the semiconductor substrate. This nesting approach allows higher integration density by stacking functional elements vertically, effectively solving the contradiction between integration density and device complexity.
2Productivity
If design rules are reduced to increase integration, then more devices fit in smaller area, but fabrication difficulty and yield decrease
Solution Approach 1:
By moving to vertical channel transistors, the patent achieves higher integration density without requiring proportional reduction in lateral design rules. The vertical dimension provides additional space for device stacking, allowing increased integration while maintaining more relaxed lateral fabrication precision requirements.
3Adaptability or versatility
If more wiring layers are added to improve connectivity, then wiring freedom increases, but device complexity and resistance increase
Solution Approach 1:
The patent utilizes vertical interconnect structures and through-substrate vias to provide additional wiring pathways in the vertical dimension. This reduces the need for excessive lateral wiring layers, achieving wiring freedom while controlling device complexity and resistance.
4Productivity
If transistor size is reduced to increase integration, then more transistors per area, but resistance and current driving capability worsen
Solution Approach 1:
The vertical channel structure increases the effective channel area without reducing the transistor footprint. By extending the channel vertically, the patent maintains or improves current driving capability and electrical performance while achieving higher integration density through compact lateral dimensions.
Solution Approach 2:
The patent employs composite material structures including stacked active regions with different semiconductor materials or doped regions, enabling optimized electrical performance in vertical channel transistors. This composite approach maintains reliability while achieving high integration density.
Data Source
AI summary
Disclosed is a semiconductor memory device including a lower structure and an upper structure on the lower structure. The upper structure includes a first substrate, an upper wiring line on the first substrate, a lower power line in a lower portion of the first substrate, and a first bonding pad between the lower power line and the lower structure. The lower power line and the first bonding pad are electrically connected to each other. The upper structure is electrically connected through the first bonding pad to the lower structure.