Vertical Channel Memory Bonding for Higher-Density Semiconductor Layouts
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Solution Overview
Problem
The integration of two-dimensional memory devices is limited by the need for high-priced equipment and limited chip area, hindering the achievement of high performance and economic feasibility.
Innovation Solution
A method of fabricating a semiconductor device with a vertical channel transistor, involving the formation of back gate electrodes, active patterns, word lines, bit lines, and capacitors, and utilizing a direct bonding method to integrate memory cell and peripheral regions, reducing the need for additional contact regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional memory device integration is increased using fine pattern formation technology, then integration density improves, but equipment cost increases and chip die area is limited
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertical channel transistors. The vertical channel extends in the thickness direction of the substrate, allowing multiple memory cells to be stacked vertically. This dimensional change enables higher integration density without requiring additional fine pattern formation equipment, as the increased capacity comes from vertical stacking rather than horizontal miniaturization.
Solution Approach 2:
The patent implements a stacked memory structure where multiple memory cell regions are vertically nested on top of each other. Each memory cell contains vertically stacked components including active patterns, word lines, bit lines, and capacitors arranged in multiple tiers. This nesting approach allows multiple functional layers to occupy the same horizontal footprint, dramatically increasing integration density without expanding chip area or requiring more expensive patterning equipment.
2Quantity of substance
If two-dimensional memory device integration is increased, then integration density improves, but chip die area becomes limited
Solution Approach 1:
The patent utilizes the vertical dimension by implementing vertical channel transistors where the channel extends through the thickness of the substrate. This allows memory cells to be arranged in multiple vertical layers, effectively using the third dimension to increase storage capacity. The horizontal chip die area remains constant while the vertical stacking multiplies the functional capacity, decoupling integration density from chip area constraints.
Solution Approach 2:
Multiple memory cell regions are vertically stacked and nested within the same horizontal footprint. Each stack contains multiple tiers of active patterns, word lines, and bit lines arranged vertically. This nested configuration allows the memory device to achieve high integration density by utilizing vertical space rather than expanding horizontal chip area, directly addressing the limitation of fixed die area.
3Quantity of substance
If vertical channel transistor structure is used, then integration density improves, but device complexity increases
Solution Approach 1:
The fabrication process is divided into distinct sequential stages: forming the buried insulating layer, creating the active layer, patterning first and second active patterns on opposite sides of the vertical channel, depositing word lines and bit lines in specific sequences, and stacking multiple memory cell regions. Each stage builds upon the previous one with clear process boundaries, making the complex vertical structure manufacturable through systematic step-by-step fabrication rather than requiring simultaneous complex operations.
Data Source
AI summary
A method of fabricating a semiconductor device may use, as an internal contact region, a region in which a memory cell region overlaps a core and/or peripheral region by bonding at least a partial region of the memory cell region to at least a partial region of the core and/or peripheral region by a direct bonding method, and thus, even when an additional contact region is secured outside the memory cell region to be smaller, signals and/or power may be transmitted between the memory cell region and the core and/or peripheral region.