Vertical Memory Transistor Structure With Buried Bit Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge is to increase the storage density of memory without degrading the performance of transistors, which is limited by the narrow-width and short-channel effects as the channel size of planar transistors is reduced.
Innovation Solution
A method is developed to form a semiconductor structure with buried bit lines and vertical transistors, where the sacrificial layer is replaced by bit lines, and the active layer is patterned to form active pillars, reducing the risk of collapse and allowing for a smaller transistor size without decreasing the channel width, thereby increasing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the channel size of planar transistors is reduced to increase storage density, then the storage density of memory is increased, but the performance of transistor is degraded by narrow-width effect and short-channel effect
Solution Approach 1:
The patent transitions from planar transistors to vertical transistors, changing the dimensional orientation of the channel from horizontal to vertical. This allows the channel length to extend in the vertical direction while maintaining adequate channel width in the horizontal plane, thereby increasing storage density without suffering from short-channel effects that plague scaled-down planar devices.
Solution Approach 2:
The patent segments the transistor structure into distinct vertical layers including the active layer, sacrificial layer, and bit line structures. This segmentation enables independent optimization of each layer's function and facilitates the formation of buried bit lines that connect to the bottom of the vertical transistor channel, resolving the conflict between density and performance.
2Quantity of substance
If the size of transistor is decreased to increase storage density, then the storage density of memory is increased, but the manufacturing complexity increases due to narrow-width and short-channel effects
Solution Approach 1:
By stacking transistor components vertically rather than scaling them horizontally, the invention reduces the footprint area occupied by each transistor while maintaining functional dimensions. This vertical stacking approach simplifies the overall device layout and reduces manufacturing complexity associated with sub-micron planar scaling.
Solution Approach 2:
The sacrificial layer is formed and positioned before the active layer is patterned. This preliminary action enables subsequent patterning steps to proceed with better control and reduced complexity, as the sacrificial layer serves as a template that guides the formation of the active region and buried bit lines.
3Area of moving object
If the active layer is patterned to form active pillars, then the transistor area is reduced, but the risk of collapse of pillars increases
Solution Approach 1:
The sacrificial layer is formed and positioned before the active layer is patterned. This preliminary structure provides mechanical support during the patterning process and maintains pillar stability. The sacrificial layer acts as a temporary scaffold that prevents collapse of the patterned active pillars, which can later be removed or integrated into the final device structure.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the transistor. The active layer is formed with specific thickness and composition optimized for vertical pillar formation, while the sacrificial layer provides localized support where needed during processing. This local differentiation of material properties enhances pillar stability without increasing overall transistor area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a higher storage density of memory without degrading transistor performance by reducing the transistor area and maintaining channel width, thus enhancing the integration level of the semiconductor structure.
Implementation Method 1
the active layer is patterned to form the active pillars
Implementation Method 2
the semiconductor pillars are formed on the top of the active pillars by an epitaxial growth process in the subsequent process
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A semiconductor structure and a method for forming the same, and a memory and a method for forming the same are provided. The method for forming the semiconductor structure includes: providing a substrate, in which a sacrificial layer and an active layer on the sacrificial layer are formed on the substrate; patterning the active layer and the sacrificial layer to form grooves which divide the active layer and the sacrificial layer into a plurality of active areas; filling the grooves to form a first isolation layer surrounding the active areas; patterning the active layer in the active areas to form a plurality of separate active patterns; removing the sacrificial layer via openings between adjacent active patterns to form gaps between bottoms of the active patterns and the substrate; forming bit lines in the gaps; and forming semiconductor pillars on partial tops of the active patterns. By the method, a planar size of a transistor can be reduced, and a storage density of the memory can be increased.