Vertical Ferroelectric Memory Cell Structure for Density and Current
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving increased integration and improved electrical properties, primarily due to limitations in pattern formation technology which affect the area occupied by unit memory cells.
Innovation Solution
The semiconductor memory device incorporates a three-dimensional cell array structure with bit lines, word lines, active patterns, and ferroelectric data storage patterns, featuring vertical and horizontal parts, and source lines, allowing for increased integration and improved electrical properties through the use of ferroelectric field effect transistors and specific materials like indium-gallium-zinc oxide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional two-dimensional planar semiconductor devices are used, then manufacturing process is simpler, but integration density and electrical properties deteriorate
Solution Approach 1:
The patent transitions from conventional two-dimensional planar memory cells to three-dimensional vertical memory cells. The active pattern extends vertically with channel regions at different heights, allowing multiple storage nodes to be stacked above each other. This dimensional transition increases integration density by utilizing the vertical space rather than only horizontal plane, resolving the contradiction between manufacturing precision (integration density) and device complexity.
2Manufacturing precision
If unit memory cell area is reduced to increase integration, then integration density improves, but electrical properties such as operating current deteriorate
Solution Approach 1:
By extending the active pattern vertically with multiple channel regions at different heights, the invention increases the effective channel volume without reducing the horizontal footprint. This allows integration density to improve while maintaining sufficient channel cross-section area for good electrical properties, resolving the contradiction between integration density and electrical performance.
Solution Approach 2:
The patent employs ferroelectric material layers in combination with semiconductor channel materials to form composite memory cell structures. The ferroelectric layer provides non-volatile storage capability while the semiconductor channel ensures good electrical conductivity, achieving both high integration density and reliable electrical properties simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances integration and electrical performance by enabling higher density memory cell arrays with improved operating currents and memory windows, while maintaining non-volatile data storage capabilities.
Implementation Method 1
first ferroelectric patterns between the first word lines and the first vertical part of the active patterns; second ferroelectric patterns between the second word lines and the second vertical part of the active patterns
Data Source
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AI summary
A semiconductor memory device is provided. The semiconductor memory device includes: a bit line (BL) that extends in a first direction; first (WL1) and second (WL2) word lines that extend in a second direction and cross the bit line; an active pattern (AP) on the bit line between the first and second word lines, the active pattern including first (VP1) and second (VP2) vertical parts that are opposite to each other, and a horizontal part (HP) that extends between the first and second vertical parts; a first data storage pattern (DSP2) between the first word line and the first vertical part of the active pattern; a second data storage pattern (DSP1) between the second word line and the second vertical part of the active pattern; and a source line connected to the active pattern, the source line (SL2) extending the first direction and crossing the first word line and the second word line.