Vertical Memory Cell Etching Precision via Segmented Sacrificial Layers
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Solution Overview
Problem
Current methods for forming arrays of memory cells with programmable charge-storage transistors face challenges in achieving precise etching and uniformity of charge-storage and sacrificial materials, leading to inefficiencies in the formation of vertical memory cell strings.
Innovation Solution
The method involves forming a stack with alternating insulative and wordline tiers, channel openings through which charge-storage material is deposited, and sacrificial material is etched and removed to create a charge-blocking region, followed by the formation of insulative charge-passage and channel materials, enabling the formation of elevationally-extending memory cells with a programmable charge-storage transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used for charge-storage and sacrificial materials, then the manufacturing process is simpler, but the etching precision and uniformity deteriorate
Solution Approach 1:
The patent divides the etching process into multiple sequential steps with different etchants: first etching charge-storage material (e.g., silicon nitride with BF3/SF6 plasma), then etching sacrificial material (e.g., silicon oxide with HF vapor). This segmentation allows each material to be etched with optimal precision while maintaining manageable process complexity through systematic breakdown.
Solution Approach 2:
The patent introduces sacrificial material as an intermediary component that enables precise formation of the charge-blocking region. The sacrificial material is deposited, etched selectively, and then removed, serving as a temporary structure that facilitates precise charge-blocking region formation without directly etching the charge-storage material, thereby improving overall etching precision.
2Speed
If charge-storage material is etched aggressively to improve speed, then the etching speed increases, but the uniformity and precision of charge-storage material formation deteriorates
Solution Approach 1:
The etching process is segmented into distinct stages: charge-storage material etching followed by sacrificial material etching. Each stage uses optimized etchants and parameters tailored to the specific material, allowing high speed in each step while maintaining overall precision through the systematic sequence rather than attempting single-step aggressive etching.
Solution Approach 2:
The patent employs selective etching sequences where the outcome of the first etching step (charge-storage material removal) provides feedback for the second step (sacrificial material removal). This sequential feedback mechanism ensures that etching proceeds with appropriate speed and precision at each stage, preventing over-etching or non-uniform formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the efficient and uniform formation of vertical memory cell strings, enhancing the programmability and retention characteristics of memory cells by ensuring precise control over the charge-blocking region and material etching processes.
Implementation Method 1
Elevationally-outer portions of each of the charge-storage material and the sacrificial material that are within the channel openings are etched
Implementation Method 2
Charge-storage material is formed within the channel openings elevationally along the alternating tiers and the select gate tier
Data Source
AI summary
A method of forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising alternating insulative tiers and wordline tiers. A select gate tier is above an upper of the insulative tiers. Channel openings extend through the alternating tiers and the select gate tier. Charge-storage material is formed within the channel openings elevationally along the alternating tiers and the select gate tier. Sacrificial material is formed within the channel openings laterally over the charge-storage material that is laterally over the select gate tier and that is laterally over the alternating tiers. Elevationally-outer portions of each of the charge-storage material and the sacrificial material that are within the channel openings are etched. After such etching, the sacrificial material is removed from the channel openings. After such removing, insulative charge-passage material then channel material are formed within the channel openings laterally over the charge-storage material that is laterally over the wordline tiers. The wordline tiers are formed to comprise control-gate material having terminal ends corresponding to control-gate regions of individual memory cells and to have a charge-blocking region of the individual memory cells laterally between the charge-storage material and individual of the control-gate regions.