Vertical 3D Memory Cell Structure for Flash Miniaturization
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Solution Overview
Problem
Conventional NAND-type flash memories face limitations in miniaturization due to short channel effects, difficulty in forming shallow junctions, hot electron injection, and intercell interference caused by capacitive coupling between neighboring memory cells.
Innovation Solution
A semiconductor integrated circuit with a memory cell structure featuring a semiconductor pillar, a floating gate that circumferentially covers the pillar via an insulating layer, and a control gate that circumferentially covers the pillar and floating gate, reducing short channel effects and intercell interference through electrostatic shielding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the channel length is shortened to increase integration density, then the memory cell size is reduced, but short channel effects cause threshold voltage fluctuation and current leakage
Solution Approach 1:
The patent transitions from planar 2D memory cells to vertical 3D memory cells with channel lengths extending in the vertical dimension. This allows shorter effective channel lengths for high integration while maintaining stable threshold voltages through the vertical field effect transistor structure with controlled electric fields.
Solution Approach 2:
The patent implements a nested structure where the control gate circumferentially covers the floating gate, which in turn covers the semiconductor pillar. This nested configuration creates electrostatic shielding that suppresses hot electron injection and stabilizes threshold voltage while enabling vertical channel structures.
2Ease of manufacture
If conventional planar structures are used, then manufacturing is simpler, but intercell interference occurs due to capacitive coupling between adjacent cells
Solution Approach 1:
The patent eliminates intercell interference by transitioning from planar 2D adjacent cell arrangements to vertical 3D structures where cells are stacked in the vertical dimension. This spatial separation in the vertical direction removes parasitic capacitive coupling between cells while maintaining manufacturing feasibility through standard vertical processing techniques.
3Reliability
If floating gate structures are used for nonvolatile storage, then storage reliability is improved with high barrier height, but neighboring cells experience capacitive coupling causing intercell interference
Solution Approach 1:
The patent resolves the intercell interference issue while preserving floating gate reliability by stacking memory cells vertically in the third dimension. This vertical arrangement physically separates cells to eliminate parasitic capacitive coupling, while each cell maintains its high-barrier-height poly silicon floating gate structure for reliable nonvolatile storage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables miniaturization of memory cells, suppresses intercell interference, and allows for multivalued storage by adjusting the charge amount on the floating gate, improving storage reliability and reducing production costs.
Implementation Method 1
a control gate that circumferentially covers the side face of the semiconductor pillar or covers a part thereof via an insulating layer on the outer circumference of the semiconductor pillar and that circumferentially covers the side face of the floating gate
Implementation Method 2
via an insulating layer on the outer circumference of the semiconductor pillar
Data Source
AI summary
Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method of producing the semiconductor integrated circuit. A memory cell 1 in the semiconductor integrated circuit is provided with: a semiconductor pillar 2 that serves as a channel; a floating gate 5 that circumferentially covers the semiconductor pillar 2 via a tunnel insulation layer 6 on the outer circumference of the semiconductor pillar 2; and a control gate 4 that circumferentially covers the semiconductor pillar via an insulating layer 8 on the outer circumference of the semiconductor pillar 2, and that circumferentially covers the floating gate 5 via an insulating layer 7 on the outer circumference of the floating gate.