Vertical Memory Cell Architecture for Higher Density and Lower Leakage
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to increased complexity and cost as feature sizes approach a lower limit, limiting memory density and efficiency.
Innovation Solution
Implementing vertical transistors with multi-gate structures, such as GAA, tri-gate, and double-gate transistors, and arranging memory cell arrays and peripheral circuits on different wafers for bonding, reducing transistor area and simplifying interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but fabrication complexity and cost increase as feature sizes approach a lower limit
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to vertical (3D) transistor structures, enabling memory scaling in the vertical dimension rather than continuing to scale lateral feature sizes. This dimensional change allows continued memory density improvement while avoiding the fabrication complexity and cost penalties that arise when planar feature sizes approach physical limits.
2Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density is improved, but process and fabrication techniques become challenging and costly
Solution Approach 1:
By moving to vertical transistors and 3D stacked architectures, the patent enables memory scaling without requiring increasingly complex and costly planar fabrication processes. The vertical structure allows standard fabrication techniques to be applied in the vertical dimension, maintaining manufacturing ease while achieving higher density.
3Area of moving object
If memory cells use vertical transistors with multi-gate structures, then transistor area is reduced and memory density is enhanced, but device structure complexity increases
Solution Approach 1:
The vertical transistor structure with multi-gate configurations (such as gate-all-around or gate-tri-around) controls the channel in the vertical dimension, achieving superior gate control and reduced area occupation. The vertical orientation allows multiple gates to wrap around the channel, providing enhanced control without proportionally increasing the planar footprint.
Solution Approach 2:
The vertical transistor employs composite material structures including semiconductor layers, dielectric layers, and conductive gates arranged in vertical stacks. This composite architecture enables compact integration while maintaining electrical performance, reducing the area required per transistor.
4Manufacturing precision
If memory cell arrays and peripheral circuits are arranged on different wafers and bonded, then interconnect structures are simplified and alignment precision is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent divides the memory device into separate functional modules: memory cell arrays fabricated on one wafer and peripheral circuits on another wafer. These segmented modules are then bonded together through precise alignment and bonding processes. This segmentation allows each module to be optimized and fabricated independently, improving overall alignment precision and manufacturing flexibility.
Solution Approach 2:
The bonding interface between separate wafers acts as an intermediary connection, enabling modular integration of memory arrays and peripheral circuits. This intermediary bonding structure simplifies interconnect design compared to monolithic integration, as it allows independent optimization of each module while achieving precise alignment through the bonding process.
Data Source
AI summary
A semiconductor device and method for forming thereof is provided. The semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes memory cells each having a vertical transistor and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor layer extending along a vertical direction and a gate structure coupled to the semiconductor layer. A leakage value of the semiconductor layer is lower than a pico-ampere. The first semiconductor structure is bonded with the second semiconductor structure, and the vertical transistor is between the peripheral circuit and the storage unit.