2T Vertical Memory Cell With Memristor Element
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Solution Overview
Problem
Conventional volatile memory devices face challenges in reducing memory cell size for increased storage density due to physical limitations and data retention issues related to charge leakage.
Innovation Solution
The development of a memory device with two-transistor (2T) memory cells that store information based on resistance states, using a cross-point gain cell structure with a single access line and data line for read/write operations, improving retention and reducing power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional capacitor-based memory cell structures are used to store information as charge, then data storage function is achieved, but memory cell size cannot be reduced further due to physical limitations and charge leakage causes data retention problems
Solution Approach 1:
The patent changes the fundamental parameter of information storage from charge-based (capacitor) to resistance-based (memristor). The memristor device exhibits different resistance states (high resistance ratio HRR) that can represent binary data, eliminating charge leakage issues and enabling smaller cell dimensions while maintaining data retention reliability.
Solution Approach 2:
The patent replaces the electrical charge storage mechanism (capacitor) with a resistive state mechanism (memristor). The memristor uses ion migration and filament formation to create stable resistance states, substituting the unstable charge-based system with a more reliable resistance-based system that does not suffer from leakage.
2Productivity
If memory cell size is reduced to increase storage density, then device storage density improves, but physical limitations and fabrication constraints challenge further shrinkage
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to a vertical 3D stacked architecture. Multiple memory stacks are arranged vertically, allowing significant increase in storage density without further reducing the lateral footprint of individual cells. This dimensional change bypasses the physical limitations of continued 2D scaling.
Solution Approach 2:
The patent implements a stacked memory architecture where multiple memory cells are vertically nested within a single footprint area. The cross-point gain cell structure allows multiple stacks to be integrated in the vertical dimension, effectively nesting storage capacity within a compact lateral footprint.
3Ease of manufacture
If conventional memory structures are used, then fabrication processes are well-established, but further scaling faces fabrication constraints
Solution Approach 1:
The patent divides the memory structure into discrete vertical stacks that can be independently formed and controlled. Each stack consists of alternating dielectric and conductive layers that can be fabricated using standard semiconductor processing techniques, allowing modular scaling and integration while maintaining fabrication ease.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a smaller memory device footprint and enhanced data retention by storing information as resistance states instead of charge, addressing the limitations of conventional technologies.
Implementation Method 1
The memory element can have different resistance states. A different resistance state can represent a different value of information stored in the memory element.
Data Source
AI summary
Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a conductive region; a memory cell including a memory element, a first portion, a second portion, a dielectric portion, and a third portion; and a data line formed over the second and third portions of the memory cell. The memory element is formed over the conductive region. The first portion is formed over the memory element and includes a first conductive material. The second portion is formed over the first portion and includes a second conductive material. The dielectric portion includes a first side adjacent the memory element, the first portion, and the second portion. The third portion includes a third conductive material and is adjacent a second side of the dielectric portion and separated from the memory element, the first portion, and the second portion by the dielectric portion.