Self-Aligned Vertical Memory Cell for DRAM Scaling
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Solution Overview
Problem
The increasing density and decreasing size of memory structures in semiconductor devices make precise mask alignment between transistor and capacitor fabrication processes challenging, leading to difficulties in forming efficient memory cells, particularly in DRAM cells with a 1T-1C configuration.
Innovation Solution
The development of self-aligned vertical thin film transistors and capacitors within a trench structure, where the transistor is fabricated above or below the capacitor, eliminating the need for precise mask alignment and allowing for denser and smaller memory cell design, with a capacitor structure including first and second electrodes separated by a high-κ dielectric and a semiconductor material in contact with both the capacitor and bitline electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional planar memory structures are used with precise mask alignment, then manufacturing precision can be maintained, but device complexity and fabrication difficulty increase as density increases
Solution Approach 1:
The patent transitions from planar (2D) memory structures to vertical (3D) structures by stacking the transistor and capacitor in the vertical dimension. This dimensional change eliminates the need for precise lateral mask alignment between separate transistor and capacitor fabrication processes, as both structures are formed within the same vertical trench using self-aligned processes.
Solution Approach 2:
The patent merges the transistor and capacitor fabrication processes into a unified self-aligned process where both structures are formed simultaneously within the same trench. The transistor gate and capacitor electrodes share common alignment references, eliminating the need for separate mask alignment steps and reducing overall fabrication complexity.
2Area of moving object
If memory cell size is decreased to increase density, then integration density improves, but manufacturing precision requirements become more stringent
Solution Approach 1:
By moving to vertical stacking, the patent reduces the lateral footprint of memory cells while avoiding the need for proportionally tighter lateral alignment tolerances. The self-aligned vertical process maintains manufacturing precision requirements at manageable levels even as cell area decreases.
Solution Approach 2:
The self-aligned fabrication process allows the structures to align themselves during manufacturing without requiring external alignment references or complex mask alignment procedures. This self-alignment mechanism maintains precision automatically regardless of the final device size.
3Device complexity
If vertical self-aligned structures are implemented, then device complexity is reduced and scalability improves, but new fabrication challenges are introduced
Solution Approach 1:
The vertical trench structure is divided into distinct functional segments (capacitor region, transistor region, interconnect regions) that can be processed independently and then integrated. This segmentation allows complex vertical structures to be manufactured through a series of simpler, modular fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of smaller, more densely packed memory cells with improved scalability, reducing fabrication complexity and enhancing the integration density of memory structures without the need for precise alignment, thus addressing the limitations of traditional methods.
Implementation Method 1
a capacitor structure in a first portion of the vertical bore, the capacitor structure having a first electrode, a second electrode, and a high-κ dielectric between the first electrode and the second electrode
Implementation Method 2
a transistor structure in a second portion of the vertical bore, the transistor structure having a third electrode extending into the second portion of the vertical bore, a layer of semiconductor material in contact with the third electrode and in contact with the second electrode
Data Source
AI summary
An integrated circuit includes one or more layers of insulating material defining a vertical bore with a first portion and a second portion. A capacitor structure is in the first portion of the vertical bore and includes a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode. A transistor structure is in the second portion of the vertical bore and includes a third electrode extending into the second portion of the vertical bore, a layer of semiconductor material in contact with the first electrode and in contact with the second electrode, and a dielectric between the semiconductor material and the insulating material. A fourth electrode wraps around the transistor structure such that the dielectric is between the semiconductor material and the fourth electrode. The capacitor structure can be above or below the transistor structure in a self-aligned vertical arrangement.