Vertical 3D Memory Cell With Shared Read-Write Bit Line
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Solution Overview
Problem
Conventional volatile memory devices face challenges in reducing memory cell size to increase storage density due to physical limitations and fabrication constraints, and they typically lose information when power is disconnected.
Innovation Solution
The memory device employs a two-transistor (2T) structure with a floating gate or charge trap memory cell, where a single access line controls both transistors, and a single bit line pair performs both read and write operations, allowing for smaller size and efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase storage density, then storage density is improved, but physical limitations and fabrication constraints are worsened
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to a three-dimensional vertical structure. The bit line extends vertically through multiple levels to access charge storage nodes at different heights, enabling stacking of memory cells in the vertical dimension. This dimensional change allows increased storage density without proportionally reducing lateral cell dimensions, thereby avoiding the worst aspects of fabrication constraints at scaled dimensions.
Solution Approach 2:
The patent implements a nested structure where the bit line passes through vertically stacked levels, with each level containing charge storage nodes and transistor components. The bit line is nested within a well structure that extends through multiple levels, and charge storage nodes are positioned at different vertical positions along the bit line. This nesting allows multiple memory cells to share common bit line infrastructure, improving density while maintaining manufacturability.
2Ease of operation
If conventional volatile memory structure is used, then operational simplicity is maintained, but information is lost when power is disconnected
Solution Approach 1:
The patent merges characteristics of volatile and non-volatile memory by combining the simple transistor-based access structure of volatile memory with charge trapping mechanisms from non-volatile memory. The charge storage nodes can trap charge in an insulating layer, providing non-volatile retention while maintaining access through standard transistor gate control. This merging allows the memory to operate like conventional volatile memory during read/write operations while retaining information without power.
Solution Approach 2:
The patent creates a multi-functional memory cell that can operate in both volatile and non-volatile modes. The same transistor and bit line structure supports both volatile operation (fast read/write with power) and non-volatile operation (retention without power). The charge storage node serves dual purposes: enabling rapid electrical access when powered and providing charge trapping for retention when unpowered, thus achieving universality across different operational requirements.
Data Source
AI summary
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple levels of two-transistor (2T) memory cells vertically arranged above a substrate. Each 2T memory cell includes a charge storage transistor having a gate, a write transistor having a gate, a vertically extending access line, and a single bit line pair. The source or drain region of the write transistor is directly coupled to a charge storage structure of the charge storage transistor. The vertically extending access line is coupled to gates of both the charge storage transistor and the write transistor of 2T memory cells in multiple respective levels of the multiple vertically arranged levels. The vertically extending access line and the single bit line pair are used for both write operations and read operations of each of the 2T memory cells to which they are coupled.