Vertical Channel Memory Cell Stacking for Dense Signal Routing
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving improved electrical characteristics and integration density as design rules shrink, particularly in the integration and operational speed of transistors with vertical channels.
Innovation Solution
The semiconductor memory device incorporates a stacked structure with first upper and lower cell structures on a peripheral structure, featuring vertical channel transistors, bit lines, word lines, and a through via for electrical connections, along with a peripheral substrate and interlayer insulating layers to enhance integration and reduce horizontal size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical channel transistors are used to increase integration density, then the number of transistors per unit area increases, but the manufacturing precision and electrical characteristics become more difficult to control
Solution Approach 1:
The patent transitions from planar transistors to vertical channel transistors, changing the dimensional orientation of the channel from horizontal to vertical. This allows the channel to extend in the vertical direction while maintaining a smaller horizontal footprint, thereby increasing integration density without sacrificing electrical characteristics control through advanced fabrication processes
Solution Approach 2:
The patent implements a stacked structure where upper cell structures are positioned above lower cell structures, with through vias connecting them. This nested arrangement allows multiple memory cell layers to be integrated within a compact vertical space, significantly increasing the quantity of storage elements per unit area while maintaining manufacturability through sequential fabrication steps
2Quantity of substance
If more memory cells are integrated in a smaller area, then integration density increases, but the horizontal size of the device decreases which complicates signal routing and electrical connections
Solution Approach 1:
The patent utilizes the vertical dimension to route signals through through vias that penetrate the substrate, connecting upper and lower cell structures. This three-dimensional routing approach eliminates the need for complex lateral signal paths, simplifying the routing architecture while enabling high integration density through vertical stacking of memory cells
Solution Approach 2:
The patent divides the memory device into separate upper and lower cell structures that can be independently fabricated and then interconnected through through vias. This segmentation allows for modular design and simplified routing within each layer, while the vertical interconnections provide straightforward pathways for signals between layers, reducing overall routing complexity
Data Source
AI summary
Provided is a semiconductor memory device. The semiconductor memory device includes a peripheral structure, a first upper cell structure on the peripheral structure, and a first lower cell structure on an opposite side of the peripheral structure from the first upper cell structure, wherein each of the first upper cell structure and the first lower cell structure includes a first active pattern perpendicular to an upper surface of the peripheral structure, a first word line adjacent to a side surface of the first active pattern and extending in a first direction parallel to the upper surface of the peripheral structure, and a first bit line electrically connected to a first end of the first active pattern and extending in a second direction intersecting the first direction.