Vertical Memory Cell Stacks for High-Density DRAM Integration
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Solution Overview
Problem
The challenge in semiconductor memory devices is achieving high integration while preventing disturbance between adjacent memory cells, which is difficult with traditional planar channel transistors, leading to the need for vertically integrated structures.
Innovation Solution
The semiconductor memory device incorporates a substrate with conductive lines, cell stacks featuring vertical transistor structures, and capacitor structures, where connection contacts electrically connect the transistors and capacitors in series, allowing for high integration and vertical alignment of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical channel transistor structures are implemented to achieve high integration, then integration density is improved, but device complexity increases
Solution Approach 1:
The patent transitions from planar channel transistors to vertical channel transistors, changing the dimensional orientation of the channel from horizontal to vertical. This allows multiple transistor structures to be stacked in the vertical direction, significantly increasing integration density while managing complexity through systematic vertical stacking of identical structural units.
Solution Approach 2:
The vertical channel transistor structure is divided into multiple discrete components including channel layers, gate electrodes, gate dielectric layers, and connection contacts arranged in distinct vertical segments. This segmentation allows for modular fabrication and assembly, making the complex vertical structure more manageable while maintaining high integration.
2Quantity of substance
If multiple vertical transistor structures and connection contacts are stacked vertically, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
By stacking transistor structures and connection contacts in the vertical dimension rather than arranging them horizontally, the patent achieves higher integration density. The vertical stacking approach allows multiple layers to be formed through sequential deposition and etching processes, with each layer's precision requirements being managed independently through standardized fabrication techniques.
Data Source
AI summary
A semiconductor memory device including a substrate, a plurality of conductive lines extending in a first horizontal direction on the substrate and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, a first cell stack on each of the plurality of conductive lines and including a plurality of first vertical transistor structures and a plurality of first connection contacts, a second cell stack on the first cell stack and including a plurality of second vertical transistor structures and a plurality of second connection contacts, and a plurality of capacitor structures arranged on the second cell stack and connected to the plurality of first vertical transistor structures and the plurality of second vertical transistor structures.