Vertical Memory Cell Arrays with Trench Isolation
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Solution Overview
Problem
Current memory cell technologies face challenges in efficiently forming arrays of memory cells with precise control over transistor and charge storage device configurations, leading to suboptimal performance and scalability in integrated circuits.
Innovation Solution
The development of a method involving a semiconductor substrate with vertically oriented transistors and charge storage devices, where trenches are etched and conductive data/sense lines are formed within these trenches, coupled with access gate lines and dielectric materials to create efficient memory cell arrays, allowing for improved electrical coupling and isolation between cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional memory cell fabrication methods are used, then manufacturing process is simpler, but manufacturing precision and control over transistor and charge storage device configurations deteriorate
Solution Approach 1:
The fabrication process is divided into distinct stages: forming trenches in the substrate, depositing conductive materials for data/sense lines, forming dielectric layers, and creating access gate lines. Each stage independently contributes to the final precise configuration of transistors and charge storage devices, enabling better control without overwhelming complexity.
Solution Approach 2:
The patent introduces vertical dimension by forming trenches in the substrate and stacking conductive lines, dielectric layers, and gate structures vertically. This three-dimensional arrangement improves manufacturing precision for transistor and charge storage device configurations while managing fabrication complexity through systematic layering.
2Quantity of substance
If memory cell arrays are scaled up, then data storage capacity increases, but interference between adjacent memory cells increases
Solution Approach 1:
Dielectric layers are introduced as intermediary materials between adjacent conductive data/sense lines and between memory cell structures. These dielectric layers provide electrical isolation that prevents interference between adjacent memory cells, enabling scalable arrays with increased data storage capacity.
Solution Approach 2:
Trenches are formed to physically segment and isolate individual memory cell structures from one another. This segmentation creates discrete, isolated units that can be densely packed to increase storage capacity while maintaining electrical isolation to prevent interference between adjacent cells.
Data Source
AI summary
A memory cell includes a vertically oriented transistor having an elevationally outer source/drain region, an elevationally inner source/drain region, and a channel region elevationally between the inner and outer source/drain regions. The inner source/drain region has opposing laterally outer sides. One of a pair of data/sense lines is electrically coupled to and against one of the outer sides of the inner source/drain region. The other of the pair of data/sense lines is electrically coupled to and against the other of the outer sides of the inner source/drain region. An access gate line is elevationally outward of the pair of electrically coupled data/sense lines and is operatively adjacent the channel region. A charge storage device is electrically coupled to the outer source/drain region. Other embodiments and additional aspects, including methods, are disclosed.