2-Transistor Vertical Memory Cells for Compact 4F2 Storage
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Solution Overview
Problem
Conventional volatile memory devices face challenges in reducing memory cell size due to physical limitations and fabrication constraints, limiting the increase in storage density.
Innovation Solution
The development of a memory device with 2-transistor vertical memory cells that utilize a charge storage structure, such as a floating gate, allowing for a smaller 4F2 cell footprint and improved power efficiency through shared access and data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional memory cell structures are used, then fabrication constraints are easier to meet, but memory cell size cannot be reduced further due to physical limitations
Solution Approach 1:
The patent transitions from planar memory cell layouts to a vertical three-dimensional structure. The memory cell extends in the vertical dimension with stacked components including bit lines, word lines, and charge storage structures arranged vertically over the substrate, enabling further size reduction without hitting planar fabrication limits
Solution Approach 2:
The patent implements a nested structure where multiple functional elements are integrated within a compact vertical footprint. The charge storage structure is positioned between bit lines and word lines, with insulating and conducting layers nested concentrically, maximizing space utilization and reducing the overall cell dimensions
2Quantity of substance
If memory cell size is reduced to increase storage density, then device storage density increases, but power dissipation increases due to smaller cell dimensions
Solution Approach 1:
The patent combines multiple functions into shared structures. Word lines are shared between adjacent memory cells, and bit lines are positioned to access multiple charge storage structures. This merging reduces the number of independent conductors needed, lowering overall power consumption while maintaining high storage density
Solution Approach 2:
The vertical bit lines and word lines serve multiple functions: they provide electrical access to charge storage structures, act as signal transmission paths, and enable selective addressing of multiple memory cells. This multi-functionality reduces the total number of components needed, thereby reducing power dissipation
Data Source
AI summary
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line. The first access line is located on a first level of the apparatus and separated from the first channel by a first dielectric. The second access line is located on a second level of the apparatus and separated from the second channel by a second dielectric. The charge storage structure is located on a level of the apparatus between the first and second levels.