Vertical Memory Channel Alignment in Staircase Gate Structures
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity, particularly in achieving high capacity storage while maintaining efficient electrical characteristics, especially in the formation of gate electrodes and memory channels.
Innovation Solution
The semiconductor device incorporates a staircase-shaped gate electrode structure with a dummy gate electrode made of insulating material, an etch stop layer, and a memory channel structure featuring a charge storage layer and filling pattern, which allows for improved electrical connectivity and storage capacity through precise etching and layering techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If gate electrodes are stacked in a staircase shape to increase storage capacity, then data storage capacity is improved, but manufacturing precision deteriorates due to alignment difficulties
Solution Approach 1:
The etch stop layer is formed in advance on the sidewall of the gate electrode structure before forming the memory channel structure. This preliminary action provides a reference surface that guides the formation of the memory channel, ensuring accurate alignment between the staircase-shaped gate electrodes and the memory channel structure, thereby resolving the alignment precision issue while maintaining high storage capacity
Solution Approach 2:
The etch stop layer acts as an intermediary element between the gate electrode structure and the memory channel structure. It facilitates precise alignment by providing a controlled etching boundary, allowing the memory channel to be accurately positioned relative to the staircase-shaped gate electrodes without direct interaction between the two structures during the alignment process
2Quantity of substance
If etching is performed to form memory channels through gate electrode structures, then storage capacity is improved, but electrical shorts may occur due to misalignment
Solution Approach 1:
The etch stop layer is formed beforehand on the gate electrode sidewall to establish a precise etching boundary. During subsequent etching processes, this layer prevents over-etching and misalignment, ensuring that memory channels are formed at the correct positions without creating electrical shorts between adjacent gate electrodes, thus maintaining electrical connectivity reliability
Solution Approach 2:
The etch stop layer converts the potential harm of aggressive etching (which could cause misalignment and electrical shorts) into a benefit by providing a controlled stopping point. This allows deep etching to form high-capacity storage structures while the etch stop layer prevents the etching from penetrating too far and causing electrical shorts between gate electrodes
3Manufacturing precision
If dummy gate electrodes made of insulating material are used, then alignment precision is improved, but device complexity increases
Solution Approach 1:
The etch stop layer serves multiple functions simultaneously: it acts as an alignment reference for forming memory channels, prevents electrical shorts between gate electrodes, and provides a controlled etching boundary. This multi-functionality reduces the need for additional separate structures, thereby offsetting the increased complexity from using dummy gate electrodes with insulating materials
Data Source
AI summary
A vertical memory device includes a gate electrode structure on a substrate, a channel extending through the gate electrode structure, and an etch stop layer on a sidewall of the gate electrode structure. The gate electrode structure includes gate electrodes spaced apart from each other in a first direction and stacked in a staircase shape. The channel includes a first portion and a second portion contacting the first portion. A lower surface of the second portion has a width less than a width of an upper surface of the first portion. The etch stop layer contacts at least one gate electrode of the gate electrodes, and overlaps an upper portion of the first portion of the channel in a horizontal direction. The at least one gate electrode contacting the etch stop layer is a dummy gate electrode including an insulating material.