Vertical Memory Channel Materials for High Density and Current Transmission
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Solution Overview
Problem
Conventional 3D memory devices with polysilicon channel materials face challenges in increasing memory density due to defects, low electron mobility, and insufficient gate-induced drain leakage current, making them unsuitable for vertical memory strings with a large number of stacked transistors.
Innovation Solution
The use of channel materials with an electron mobility of at least 30 cm2/(V·s) and a room temperature band gap of at least 1.40 eV, such as zinc oxide or silicon carbide, combined with bottom plug materials having a band gap of less than 1.10 eV, like silicon germanium, to enhance current transmission and erase operations in vertical memory strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If polysilicon channel materials are used in vertical memory strings with increased height, then the memory density is increased, but the electron mobility is insufficient and defects increase making reliable operation difficult
Solution Approach 1:
The patent changes the material parameter from polysilicon to materials with higher electron mobility (≥30 cm²/(V·s)) and appropriate band gap (≥1.40 eV), fundamentally altering the electrical characteristics to enable reliable operation in longer vertical memory strings while maintaining increased memory density
Solution Approach 2:
The patent employs composite material structures including channel materials (zinc oxide, silicon carbide, indium phosphide, gallium arsenide) combined with bottom plug materials (silicon germanium, germanium, indium gallium arsenide) having complementary band gap properties, creating a composite system that simultaneously achieves high electron mobility, reduced defects, and sufficient GIDL current
2Ease of manufacture
If polysilicon channel materials are used, then the manufacturing process is conventional and simple, but the gate-induced drain leakage current is insufficient for erase functions
Solution Approach 1:
The patent modifies the band gap parameter of the channel material to be at least 1.40 eV, which fundamentally changes the electrical characteristics to enable sufficient gate-induced drain leakage current for effective erase operations, while bottom plug materials with band gap less than 1.10 eV further enhance the GIDL current
Solution Approach 2:
The bottom plug material acts as an intermediary element between the substrate and the channel material, providing a transition region with complementary band gap properties that enhances the gate-induced drain leakage current while maintaining the overall structure's manufacturability
3Quantity of substance
If vertical memory strings with increased height are created, then the memory density increases, but the current transmission capability becomes insufficient
Solution Approach 1:
The patent fundamentally changes the electron mobility parameter from polysilicon's ~10 cm²/(V·s) to at least 30 cm²/(V·s) in the channel material, enabling sufficient current transmission capability in longer vertical memory strings while maintaining increased memory density through the vertical architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves current transmission and reduces defects, enabling effective operation of vertical memory devices with increased memory density and enhanced gate-induced drain leakage current for improved erase functions.
Implementation Method 1
The channel material exhibits an electron mobility of at least about 30 cm2/(V·s) and a room temperature band gap of at least about 1.40 eV
Implementation Method 2
polysilicon channel materials may result in an insufficient gate-induced drain leakage ('GIDL') current for erase functions on such long vertical memory strings
Data Source
AI summary
Memory devices and electronic systems include an array of vertical memory cells positioned along respective vertical channels to define vertical memory strings. Each of the vertical channels includes a channel material exhibiting an electron mobility of at least about 30 cm2/(V·s) and a room temperature band gap of at least about 1.40 eV (e.g., zinc oxide, silicon carbide, indium phosphide, indium gallium zinc oxide, gallium arsenide, or molybdenum disulfide) and a bottom plug material exhibiting a room temperature band gap of less than about 1.10 eV (e.g., silicon germanium, germanium, or indium gallium arsenide). Methods of fabricating a memory device include forming such a bottom plug material within vertical channels and forming such a channel material electrically coupled to the bottom plug material.