Vertical Memory Channel Structure Using MILC Crystallization

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Solution Overview

Problem

Existing semiconductor devices face challenges in achieving high data storage capacity and reliability, particularly in three-dimensional memory cell arrangements.

Innovation Solution

A semiconductor device with a vertical stack of gate electrodes and channel structures featuring a channel layer with a single crystal structure and a polycrystalline central pad layer, formed through metal-induced lateral crystallization (MILC) to enhance reliability and storage capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If three-dimensional memory cell arrangement is implemented to increase storage capacity, then data storage capacity is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvedata storage capacityVSAvoidmanufacturing precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The channel structure is segmented into distinct crystalline regions (first crystalline region in the channel layer, second crystalline region in the pad layer) with different crystal structures. This segmentation allows each region to be optimized independently for its specific function while maintaining overall manufacturing feasibility in three-dimensional memory structures.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the channel structure are assigned different local qualities through distinct crystal structures. The channel layer region requires a first crystal structure optimized for charge transport, while the pad layer region requires a second crystal structure optimized for electrical contact and durability. This local quality differentiation resolves the manufacturing precision challenge by allowing region-specific optimization.

Inventive Principle:
Principle #3Local quality

2Reliability

If channel layer crystallization is enhanced to improve reliability, then device reliability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvedevice reliabilityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A seed layer is formed preliminarily on the channel layer before the final pad layer deposition. This seed layer serves as a crystallization template that guides the formation of the second crystalline region in the pad layer, ensuring proper crystal structure development without requiring complex in-situ crystallization processes during main manufacturing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The seed layer acts as an intermediary between the channel layer and the pad layer, mediating the crystallization process. It transfers the crystalline structure from the channel layer to the pad layer, enabling reliable crystallization while simplifying the overall manufacturing process by avoiding direct complex crystallization steps.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution provides improved reliability and increased data storage capacity by ensuring complete crystallization of channel layers, enhancing the operational efficiency and durability of the semiconductor device.

Implementation Method 1

performing metal-induced lateral crystallization (MILC) of the amorphous seed layer and the amorphous channel layer by heat treating/annealing

Methodology Applied
Scientific EffectMetal-induced lateral crystallization (MILC): Crystallisation

Data Source

PatentUS20250212399A1Semiconductor devices having enhanced channel structures therein and methods of manufacturing the same
Publication Date: 2025.06.26 SAMSUNG ELECTRONICS CO LTD
  • US20250212399A1 patent drawing
  • US20250212399A1 patent drawing
  • US20250212399A1 patent drawing

AI summary

A semiconductor device includes a substrate, a stack structure having a plurality of spaced-apart gate electrodes therein and extending in a vertical direction perpendicular to an upper surface of the substrate, and a plurality of channel structures extending vertically within respective channel holes, which pass vertically through the stack structure. Each of the channel structures includes: (i) a channel layer having a first crystal structure, and extending from adjacent an upper end to adjacent a lower end of a corresponding one of the channel holes, (ii) a protruding region extending from adjacent the upper end of each of the channel holes in the vertical direction, protruding from the channel layer toward a central axis of each of the channel holes, and having a second crystal structure, and (iii) a central pad layer extending inside the protruding region and having a third crystal structure, which is different from the first crystal structure.