Vertical Memory Channel Structure With High Electron Mobility Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices with nonvolatile memory technology face limitations in achieving high electron mobility, which affects the performance and efficiency of data storage and retrieval processes.
Innovation Solution
A semiconductor memory device with a vertical channel structure is developed, featuring a multi-layered channel structure comprising a core insulating layer, a first channel layer with higher electron mobility, a second channel layer with even higher mobility, a tunnel insulating layer, and a charge storage layer, alternately stacked with interlayer insulating and sacrificial layers, enhancing electron mobility and electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single-layer channel structure is used, then the device structure is simple, but the electron mobility is insufficient
Solution Approach 1:
The channel layer is segmented into multiple sub-layers (first channel layer and second channel layer) with different materials and electron mobilities. This segmentation allows each layer to contribute differently to charge transport, with the high-electron-mobility layer providing efficient conduction paths while the low-electron-mobility layer provides charge trapping sites, thereby resolving the contradiction between maintaining structural simplicity and achieving high electron mobility.
Solution Approach 2:
The patent employs composite material structure by combining different semiconductor materials with distinct electron mobility characteristics in the channel layer. The first channel layer uses a material with higher electron mobility (e.g., SiGe) while the second channel layer uses a material with lower electron mobility (e.g., Si), creating a composite channel structure that leverages the advantages of both materials to achieve enhanced overall electron mobility while maintaining nonvolatile memory functionality.
2Reliability
If a multi-layer channel structure with different electron mobilities is implemented, then electron mobility and electrical characteristics are enhanced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies preliminary action by forming the blocking insulating layer, charge storage layer, and tunnel insulating layer on the hole sidewalls before forming the channel layers. This sequence ensures that the complex multi-layer structure is built systematically, with each layer prepared in advance according to its specific requirements, thereby managing manufacturing complexity while achieving the desired electrical characteristics.
Solution Approach 2:
The manufacturing process utilizes parameter changes by controlling the deposition conditions, material composition ratios, and thickness parameters of each channel layer to achieve the desired electron mobility differentiation. By precisely adjusting these parameters during fabrication, the patent achieves enhanced electrical characteristics while managing the complexity of the multi-layer manufacturing process.
Data Source
AI summary
Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.