Vertical Memory Device Channel Pad Segmentation for Integration Density
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Solution Overview
Problem
There is a growing demand for semiconductor devices with higher integration density to accommodate the increasing demand for smaller, high-capacity electronic products, which existing technologies have not adequately addressed in terms of vertical-type memory devices.
Innovation Solution
A vertical-type memory device is designed with a stacked structure of gate electrodes and channel structures, including alternating n-type and p-type impurity regions in the channel pads, allowing for enhanced integration density and electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a vertical-type memory device is designed with stacked gate structures to increase integration density, then the integration density is improved, but the electrical properties (electron and hole transfer efficiency) deteriorate
Solution Approach 1:
The channel pad is segmented into distinct first and second pad regions with different impurity types (n-type and p-type respectively). This segmentation allows independent optimization of electron and hole transfer paths, resolving the contradiction by maintaining high integration density through vertical stacking while improving electrical properties through specialized regional structures that facilitate efficient carrier transport.
Solution Approach 2:
Different regions of the channel pad are assigned different local qualities through selective impurity doping. The first pad region contains n-type impurities optimized for electron transfer, while the second pad region contains p-type impurities optimized for hole transfer. This local quality differentiation enables the structure to maintain high integration density while achieving excellent electrical properties in each specific region.
2Quantity of substance
If channel structures are made to penetrate through multiple stacked gate structures, then the integration density is improved, but the manufacturing complexity increases
Solution Approach 1:
Impurities are introduced into the channel pad structure at an early stage during the formation of the channel layer, before the gate structures are fully stacked. This preliminary action simplifies subsequent manufacturing steps by pre-establishing the doping profile needed for differentiated pad regions, thereby reducing overall manufacturing complexity while maintaining high integration density.
Solution Approach 2:
The channel structures are designed to penetrate through and connect multiple stacked gate structures in a nested configuration. The channel layer is formed first, then gate structures are stacked around it, with impurity regions embedded within the channel pad. This nesting approach achieves high integration density while managing manufacturing complexity through a systematic layering process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves improved integration density and electrical performance by enabling efficient electron and hole transfer paths between channel structures, facilitating better data erasure operations in memory cells.
Implementation Method 1
The first channel structures each may include a first channel layer penetrating the first gate structure, and a first channel pad disposed on the first channel layer and including a first pad region including n-type impurities and a second pad region including p-type impurities
Data Source
AI summary
A vertical-type memory device includes: a first gate structure including first gate electrodes spaced apart from each other and stacked on a substrate; first channel structures penetrating through the first gate structure and being in contact with the substrate; a second gate structure including second gate electrodes spaced apart from each other and stacked on the first gate structure; and second channel structures penetrating through the second gate structure and being in contact with the first channel structures. The first channel structures each may include a first channel layer penetrating the first gate structure, and a first channel pad disposed on the first channel layer and including a first pad region including n-type impurities and a second pad region including p-type impurities.