Vertical Memory Channel Segmentation for Multi-Bit Storage
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Solution Overview
Problem
Current semiconductor devices face limitations in increasing data storage capacity and electrical characteristics, particularly in vertical memory devices where improving multi-bit level cell (MLC) structures is essential for enhanced performance.
Innovation Solution
The vertical memory device incorporates a memory channel structure extending vertically on a substrate, with division layers and a gate electrode structure that includes a filling pattern, channel, and charge storage structure, allowing for a multi-bit level cell (MLC) configuration by dividing the charge storage and channel structures, enabling improved electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a vertical memory device uses a conventional single-bit structure, then the device complexity is low, but the data storage capacity is limited
Solution Approach 1:
The charge storage structure is divided into multiple charge storage patterns (first charge storage pattern, second charge storage pattern, third charge storage pattern) along the vertical channel, enabling multi-bit storage. The gate electrode structure is segmented into multiple gate electrodes (first gate electrode, second gate electrode, third gate electrode) that can independently control different charge storage regions,实现ing independent programming and reading of multiple bits within a single vertical channel structure.
Solution Approach 2:
The patent transitions from a conventional planar single-bit structure to a vertical three-dimensional structure with multiple charge storage patterns stacked along the vertical direction. This dimensional change allows multiple bits to be stored within a single vertical channel by utilizing the vertical space, thereby increasing storage capacity without proportionally increasing device footprint or complexity.
2Quantity of substance
If the charge storage structure is divided into multiple patterns for MLC configuration, then the data storage capacity increases, but the manufacturing precision requirements increase
Solution Approach 1:
Multiple charge storage patterns are nested within a single vertical channel structure, with each charge storage pattern surrounded by its own gate electrode. This nested configuration allows multiple storage elements to share common structural components (channel, tunnel insulation, blocking insulation), reducing the number of independent manufacturing steps and lowering precision requirements compared to fully separate structures.
Solution Approach 2:
The patent merges multiple charge storage patterns and gate electrodes into a single integrated vertical memory cell structure. The tunnel insulation and blocking insulation layers are shared across multiple charge storage patterns, and the gate electrodes are formed in a unified process sequence, consolidating multiple functions into a single manufacturable structure that reduces overall manufacturing complexity and precision demands.
3Reliability
If multiple gate electrodes are used to control divided charge storage patterns, then the electrical characteristics improve, but the device complexity increases
Solution Approach 1:
Each gate electrode serves multiple functions: it controls the corresponding charge storage pattern for programming, provides electrical isolation between adjacent charge storage patterns, and participates in read operations. This multi-functionality reduces the need for additional specialized components, allowing the gate electrode structure to enhance electrical characteristics without proportionally increasing device complexity.
Solution Approach 2:
The gate electrode structure is segmented into multiple independently controllable gate electrodes, each associated with a specific charge storage pattern. This segmentation enables independent programming and reading of multiple bits within a single vertical channel, improving electrical characteristics and storage capacity while maintaining a relatively compact structure through the shared vertical channel architecture.
Data Source
AI summary
A vertical memory device includes a memory channel structure disposed on a substrate, a plurality of division layers disposed on the substrate and a gate electrode structure. The memory channel structure extends in a vertical direction substantially perpendicular to an upper surface of the substrate. The division layers contact the memory channel structure, respectively. The gate electrode structure contacts a sidewall of the memory channel structure, which may include a filling pattern, a channel disposed on a sidewall of the filling pattern and a charge storage structure disposed on an outer sidewall of the channel and sidewalls of the division layers, each of which extends through a portion of the charge storage structure and a portion of the channel. Each of the charge storage structure and the channel is divided into two parts by the division layers.