Vertical Memory Channel Connection via Support Pattern
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Solution Overview
Problem
In VNAND flash memory devices, the bending of channel holes makes it difficult to connect channels to substrates as the stack number of mold structures increases, hindering the formation of a stable electrical connection.
Innovation Solution
A vertical memory device design featuring sequentially stacked impurity regions, a gate electrode structure, and a charge storage structure, with a support pattern between the impurity regions to ensure electrical connectivity, and a method involving etch stop layers, sacrificial layers, and insulation layers to form channels and gate electrodes, allowing for direct contact between the channel and impurity regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the stack number of mold structure increases to improve storage capacity, then the channel hole becomes bent making it difficult to connect channel to substrate
Solution Approach 1:
The patent segments the channel structure into multiple parts: a first channel portion extending from the substrate through the first impurity region, and a second channel portion extending through the gate electrode structure. The support pattern acts as an intermediate structure to bridge these segments, allowing the channel to navigate the bent path created by increased stack numbers while maintaining electrical connection to the substrate.
Solution Approach 2:
The support pattern serves as an intermediary structure between the substrate and the gate electrode structure. It provides a physical and electrical bridge that enables the channel to connect to the substrate even when the channel hole is bent due to increased stack numbers, thus resolving the connection difficulty without limiting storage capacity expansion.
2Quantity of substance
If the stack number of gate electrodes increases to improve storage capacity, then electrical connection between channel and common source line becomes unreliable
Solution Approach 1:
The support pattern is formed in advance between the first and third impurity regions before the gate electrode structure is completed. This preliminary action ensures that the electrical connection path is established early, providing a stable foundation for subsequent processing steps and ensuring reliable electrical connection regardless of the final stack number.
Solution Approach 2:
The support pattern is strategically positioned at specific locations where electrical connection is critical - between the first and third impurity regions and contacting the second impurity region. This localized placement ensures that the most critical electrical connection points are reinforced, maintaining reliability even as the overall stack number increases.
3Ease of manufacture
If dry etching process is used to remove ONO layer with spacer as mask, then substrate exposure is achieved but channel connection becomes difficult due to bending
Solution Approach 1:
The support pattern acts as an intermediary structure that decouples the ONO layer removal process from the channel-substrate connection. The dry etching process can proceed to expose the substrate using the spacer mask, and the support pattern subsequently provides the necessary bridge for channel connection, eliminating the conflict between ease of manufacture and connection precision.
Data Source
AI summary
A vertical memory device includes first, second and third impurity regions sequentially stacked in a first direction substantially perpendicular to an upper surface of a substrate, a gate electrode structure including gate electrodes spaced apart from each other in the first direction on the third impurity region, a channel extending through the gate electrode structure, the second and third impurity regions, and an upper portion of the first impurity region on the substrate in the first direction, and a charge storage structure covering a portion of an outer sidewall and a lower surface of the channel. The channel directly contacts a sidewall of the second impurity region.