3D Vertical Memory Channel Void Structure for Precise Synaptic Resistance
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Solution Overview
Problem
Existing two-terminal memory-based synaptic devices face challenges in precisely controlling resistance due to voltage-induced changes, affecting the learning rate of neuromorphic systems, and three-terminal transistor-based devices are sought to address this weakness.
Innovation Solution
A three-dimensional vertical memory device with a vertical columnar channel region having a void structure is designed, featuring a gate, source electrode, and drain electrode, which reduces electricity conductivity and power consumption by lowering the cross-sectional area of the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a two-terminal memory-based synaptic device with crossbar array is used, then the structure is simple and high-density device array can be implemented, but the resistance value changes when voltage is applied for verification, making it difficult to precisely control synaptic resistance
Solution Approach 1:
The patent transitions from a two-terminal planar memory structure to a three-terminal vertical transistor structure. This dimensional change allows the gate electrode to control the channel conductivity independently from the source and drain terminals, enabling precise resistance control without the verification voltage interference that plagues two-terminal crossbar devices.
2Reliability
If a conventional solid channel region is used, then the channel provides good electrical conductivity, but the power consumption is high
Solution Approach 1:
The patent introduces a porous structure within the channel region by forming voids or hollow spaces inside the channel material. This porous configuration reduces the amount of conductive material present, thereby lowering the overall electrical conductivity and reducing power consumption while maintaining sufficient conductivity for device operation through the surrounding solid channel walls.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces power consumption and enhances the efficiency of deep learning acceleration in synaptic arrays, enabling low-power, high-efficiency on-device training.
Implementation Method 1
a vertical columnar channel region having a void of a predetermined size therein... which causes electricity conductivity to be lowered
Data Source
AI summary
Provided is a three-dimensional vertical memory device including: a semiconductor substrate, a vertical columnar channel region provided on the semiconductor substrate and having a void of a predetermined size therein; a source electrode and a drain electrode spaced apart from each other with the channel region interposed therebetween; and a gate stack formed on the channel region.