Vertical Memory Channel Structure for Uniform Capping Layer Width
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Solution Overview
Problem
As semiconductor devices become increasingly integrated, their electrical characteristics and production yields deteriorate, necessitating techniques to improve these aspects.
Innovation Solution
The semiconductor device incorporates a source structure with multiple source layers and a gate stack structure with alternating insulating and conductive patterns, along with a memory channel structure featuring a channel layer that penetrates the gate stack and memory layers, enhancing electrical performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density of semiconductor devices is increased, then productivity and functionality are improved, but electrical characteristics and production yields deteriorate
Solution Approach 1:
The source structure is divided into multiple source layers (first source layer, second source layer, third source layer) stacked vertically. This segmentation allows each layer to contribute to current conduction independently, improving overall electrical characteristics while maintaining high integration density. The channel layer similarly penetrates through multiple memory layers, creating segmented conduction paths that enhance reliability.
Solution Approach 2:
The patent transitions from a planar two-dimensional structure to a three-dimensional vertical structure. The channel layer penetrates vertically through the gate stack structure and multiple memory layers, creating a vertical conduction path. This dimensional change allows for higher integration density while maintaining electrical performance by utilizing the vertical space efficiently.
2Productivity
If integration density of semiconductor devices is increased, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The device is segmented into modular components: multiple source layers, multiple memory layers, and a channel layer that penetrates through them. Each layer can be formed and processed independently, allowing for better control of manufacturing precision. The alternating insulating and conductive patterns in the gate stack are also segmented, enabling precise formation of each component separately.
Solution Approach 2:
The insulating and conductive patterns are formed in advance within the gate stack structure before the channel layer is formed. This preliminary action allows the channel layer to be deposited uniformly across the entire area, ensuring consistent width and improving manufacturing precision. The source layers are also prepared in advance to receive the channel layer.
3Reliability
If channel layer penetrates through gate stack and memory layers, then electrical characteristics are improved, but device complexity increases
Solution Approach 1:
The channel layer serves multiple functions simultaneously: it acts as a conduction path through the gate stack structure, connects multiple source layers, and penetrates through memory layers. By merging these functions into a single continuous structure, the patent improves electrical characteristics without proportionally increasing complexity. The gate stack structure also merges insulating and conductive patterns into a unified alternating stack.
Solution Approach 2:
The channel layer is designed as a multi-functional element that performs conduction, connection, and penetration functions. This universal structure replaces what would otherwise require multiple separate components, improving electrical characteristics while keeping the overall device complexity manageable. The source layers similarly serve multiple purposes: electrical conduction, structural support, and alignment references.
Data Source
AI summary
A semiconductor device includes a source structure comprising a first source layer, a second source layer on the first source layer, and a third source layer on the second source layer, a gate stack structure on the source structure, the gate stack structure with alternating insulating patterns and conductive patterns, and a memory channel structure penetrating the gate stack structure. The memory channel structure includes a channel layer and a memory layer surrounding the channel layer. The channel layer penetrates the memory layer and the second source layer, and a bottom surface of the channel layer is in contact with the source structure.