Vertical Non-Volatile Memory Charge Storage Segmentation

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Solution Overview

Problem

Vertical non-volatile memory devices face reliability issues due to charge loss in the extending direction of charge storage layers, which affects the coupling between adjacent memory cell transistors, limiting the integration and performance of these devices.

Innovation Solution

The implementation of charge storage layers spaced apart from each other, with specific insulation and blocking layers arranged to maintain charge integrity and improve coupling between memory cell transistors, involves a method of manufacturing that includes forming sacrificial layers, insulation patterns, and blocking insulation layers to create separated charge storage layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If charge storage layers are arranged adjacent to each other in vertical non-volatile memory devices, then integration density is improved, but charge loss occurs in the extending direction affecting reliability

Engineering Contradiction:

Improveintegration densityVSAvoidcharge retention

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The charge storage layer is divided into multiple separated segments along the extending direction, with insulating layers positioned between adjacent segments. This segmentation prevents charge loss while maintaining high integration density through optimized spatial arrangement of the divided charge storage regions.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Insulating layers are introduced as intermediary elements between adjacent charge storage layers. These insulating layers act as mediators that prevent charge leakage while allowing the charge storage layers to remain in close proximity, thus maintaining integration density without compromising charge retention reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If charge storage layers are spaced apart to prevent charge loss, then reliability is improved, but coupling between adjacent memory cell transistors deteriorates

Engineering Contradiction:

Improvecharge retentionVSAvoidcoupling between transistors

Core Design Contradiction:

ReliabilityVSStrength

Solution Approach 1:

Different regions of the charge storage structure are assigned different qualities: the charge storage layers are spaced apart in regions where charge retention is critical, while insulating layers are strategically positioned to maintain electrical coupling where needed. This local differentiation resolves the contradiction between reliability and coupling strength.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The spacing and coupling characteristics are optimized by utilizing multiple spatial dimensions. Charge storage layers are arranged in a three-dimensional configuration where vertical spacing prevents charge loss, while horizontal positioning and insulating layer placement maintain coupling between adjacent transistors through alternative conduction paths.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Reliability

If insulating and blocking layers are added to separate charge storage layers, then charge loss is reduced, but device complexity increases

Engineering Contradiction:

Improvecharge retentionVSAvoidlayer structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The insulating layers serve multiple functions simultaneously: they prevent charge loss between adjacent charge storage layers, provide structural support for the vertical architecture, and enable continued coupling between memory cell transistors. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240206180A1Vertical non-volatile memory devices and methods for manufacturing the same

Publication Date: 2024.06.20 SAMSUNG ELECTRONICS CO LTD

AI summary

A vertical non-volatile memory device may include a mold structure including first and second insulation patterns and a first gate electrode, a semiconductor pattern extending through the mold structure in a first direction, a first charge insulation layer between the first insulation pattern and the semiconductor pattern, a second charge insulation layer spaced apart from the first charge insulation layer and between the second insulation pattern and the semiconductor pattern, a charge storage layer between the first and second charge insulation layers and between the first gate electrode and the semiconductor pattern, and a first blocking insulation layer between the first gate electrode and the charge storage layer, and a first length in the first direction of the first gate electrode is shorter than a second length in the first direction of a first surface of the charge storage layer which is in contact with the first blocking insulation layer.