Vertical Memory Devices Integrating Circuit Patterns
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Solution Overview
Problem
To enhance the integration degree of VNAND flash memory devices, there is a need to reduce the area of both the cell region where memory cells are formed and the circuit region that drives these cells, while maintaining effective memory cell operation.
Innovation Solution
A vertical memory device design featuring conductive lines stacked on a substrate with semiconductor patterns and electrodes, where the circuit patterns for driving memory cells are integrated within the memory cell structures, allowing for reduced circuit region area and increased integration by using alternating layers of insulation and sacrificial materials to form molds and conductive lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of levels at which gate electrodes are stacked on a substrate increases to increase integration degree, then the integration degree is improved, but the area of cell region and circuit region increases
Solution Approach 1:
The patent merges the circuit region functions directly into the cell region by forming source and drain electrodes within the same vertical stack structure as the memory cells. The conductive lines serve dual purposes as both gate electrodes for memory cells and as gate electrodes for circuit transistors, eliminating the need for separate circuit region area.
Solution Approach 2:
The patent transitions from planar 2D layout to vertical 3D stacking, where multiple gate electrodes are stacked in the vertical direction perpendicular to the substrate. This allows multiple memory cells and circuit elements to be integrated within the same footprint area by utilizing the vertical dimension.
2Adaptability or versatility
If the area of circuit region is decreased to increase integration degree, then the integration degree is improved, but the complexity of forming circuit patterns increases
Solution Approach 1:
The conductive lines are designed to serve multiple functions: they act as gate electrodes for both memory cell transistors and circuit transistors. The same vertical stack structure houses both memory cells and circuit elements, allowing a single patterning process to define both cell and circuit regions simultaneously.
Solution Approach 2:
The substrate is divided into first and second regions, where the first region forms memory cells and the second region forms circuit elements. Both regions share the same vertical stack structure and are formed using the same alternating insulation and sacrificial layer process, simplifying the overall fabrication complexity.
Data Source
AI summary
A vertical memory device includes conductive lines on a substrate, first and second semiconductor patterns, first and second pads, first and second electrodes, a third electrode, and a first division pattern. The conductive lines are stacked in a vertical direction and extend in a first direction. The first and second semiconductor patterns extend through the conductive lines in the vertical direction. The first and second pads are formed on the first and second semiconductor patterns. The first and second electrodes are electrically connected to the first and second pads. The third electrode is electrically connected to a first conductive line of the conductive lines. The first division pattern extends in a second direction, and extends through and divides the first conductive line. In a plan view, the first and second semiconductor patterns and the first conductive line are disposed at one side of the first division pattern.