Vertical Memory Structure With Concave Stacked Side Surfaces
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing the degree of integration, particularly in transitioning from two-dimensional to three-dimensional memory cell arrays to enhance price competitiveness.
Innovation Solution
A semiconductor device with a vertical memory structure is developed, featuring a core region, channel semiconductor structure, and data storage structure, where interlayer insulating layers and gate layers are alternately stacked, and separation structures are used to create a stacked structure with concave side surfaces, allowing for increased data storage areas and improved integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a two-dimensional array of memory cells is used, then the device structure is simple, but the degree of integration is low
Solution Approach 1:
The patent transitions from a two-dimensional memory cell array to a three-dimensional vertical memory structure. The vertical memory structure extends in the vertical direction with stacked structures including interlayer insulating layers and gate layers alternately stacked, enabling increased integration density without proportionally increasing lateral footprint.
Solution Approach 2:
The vertical memory structure employs nested configurations where channel semiconductor structures are surrounded by data storage structures, which are in turn surrounded by stacked structures with alternating insulating and conductive layers. This nested arrangement maximizes space utilization and increases the quantity of storage elements within a given volume.
2Quantity of substance
If the number of data storage areas is increased, then the degree of integration is improved, but back-tunneling phenomena occur during erase operations
Solution Approach 1:
The patent divides the vertical memory structure into multiple independent data storage areas, each surrounded by its own data storage structure and controlled by separate gate layers. This segmentation isolates the electrical fields of adjacent storage elements, preventing charge leakage through back-tunneling while maintaining high integration density.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the vertical memory structure. Specifically, data storage structures are positioned at specific locations to provide localized charge confinement, and gate layers are strategically placed to create localized electric field control zones that suppress back-tunneling in high-density regions.
3Quantity of substance
If separation structures are used to create stacked structure, then data storage areas are increased, but device complexity increases
Solution Approach 1:
The stacked structures with alternating interlayer insulating layers and gate layers serve multiple functions simultaneously: they provide electrical isolation between adjacent data storage areas, act as control elements for charge injection and extraction, and form the structural framework that defines the vertical memory cells. This multi-functionality increases data storage capacity without proportionally increasing device complexity.
Data Source
AI summary
A semiconductor device includes a first stacked structure and a second stacked structure spaced apart from each other on a substrate, and a plurality of separation structures and a plurality of vertical memory structures alternately arranged between the first stacked structure and the second stacked structure in a first direction parallel to an upper surface of the substrate. Each of the first and second stacked structures includes a plurality of interlayer insulating layers and a plurality of gate layers alternately repeatedly stacked on the lower structure. Each of the vertical memory structures includes a first data storage structure facing the first stacked structure and a second data storage structure facing the second stacked structure. Side surfaces of the first and second stacked structures facing the vertical memory structures are concave in a plan view.