Vertical Memory Contact Plug Formation via Preliminary Action
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Solution Overview
Problem
The increasing height of stack structures in semiconductor devices makes it difficult to form contact plugs, which is a challenge for high integration and maintaining excellent electrical properties.
Innovation Solution
A vertical memory device is designed with a substrate having a peripheral circuit interconnection, lower word lines stacked in a staircase structure, and vertical channel structures passing through the word lines, along with cell contact plugs connected to the word lines, and alternately stacked insulating and mold patterns to facilitate efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the height of stack structure is increased for high integration, then the integration density is improved, but the difficulty of forming contact plugs increases
Solution Approach 1:
The patent applies preliminary action by forming the cell contact plug before forming the upper stack structure. The contact plug is prepared in advance at a position where it will eventually connect to the lower word line, allowing the upper stack structure to be built around it without interfering with contact plug formation. This resolves the technical contradiction by enabling high integration through stacked structures while maintaining ease of manufacture through sequential processing steps.
Solution Approach 2:
The patent segments the stack structure into distinct regions: a lower stack structure containing the contact plug connection to the lower word line, and an upper stack structure built subsequently. This segmentation allows independent optimization of each region - the lower portion can be formed with proper contact plug connections while the upper portion can be added for high integration, thus resolving the contradiction between integration density and manufacturing difficulty.
2Quantity of substance
If the height of stack structure is increased for high integration, then the integration density is improved, but the electrical properties deteriorate
Solution Approach 1:
By preparing the cell contact plug in advance before building the upper stack structure, the patent ensures proper electrical connection to the lower word line is established early. This preliminary action guarantees reliable electrical properties are maintained even as the stack structure height increases for high integration, as the critical contact connection is formed when access to the lower word line is still straightforward.
Solution Approach 2:
The patent applies local quality by ensuring the lower portion of the stack structure has optimized electrical connection characteristics through proper contact plug formation, while the upper portion can be densely integrated. This localized optimization of electrical properties in the critical connection region maintains reliability while allowing high integration in other regions.
Data Source
AI summary
A vertical memory device includes a substrate having a peripheral circuit interconnection, lower word lines stacked on the substrate, vertical channel structures passing through the lower word lines, a first cell contact plug including a bottom end lower than a bottom surface of a first lower word line and being connected to the first lower word line, and lower insulating layers and first lower mold patterns positioned beneath the first lower word line and stacked alternately on each other from the substrate.