Vertical Nonvolatile Memory Contact Stacking for Smaller Chip Area
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Solution Overview
Problem
The challenge lies in reducing the size of nonvolatile memory devices while maintaining their storage capacity and efficiency, particularly in the context of vertical channel structures which require innovative manufacturing methods to minimize chip size and optimize integration.
Innovation Solution
The proposed solution involves a vertical nonvolatile memory device with a substrate having a cell array and extension areas, featuring a vertical channel structure with alternating gate electrode layers and interlayer insulating layers, along with a contact separation layer that separates metal contacts into lower and upper segments, allowing for a stacked configuration that reduces the extension area size by half.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical channel structures are used to increase integration, then storage capacity is improved, but chip size reduction becomes more difficult
Solution Approach 1:
The patent transitions from planar transistor structures to vertical transistor structures, moving the channel orientation from the plane of the substrate into the third dimension. This vertical channel structure allows storage capacity to increase while managing chip size by utilizing vertical space rather than horizontal space.
Solution Approach 2:
The patent implements a stacked structure where gate electrode layers and interlayer insulating layers are alternately stacked along the side wall of the vertical channel structure. This nested arrangement allows multiple functional layers to be integrated within the vertical channel structure, increasing storage capacity without proportionally increasing chip area.
2Area of stationary object
If extension area is reduced to minimize chip size, then manufacturing complexity increases
Solution Approach 1:
The patent divides the metal contacts into lower metal contacts and upper metal contacts using a contact separation layer. This segmentation allows the extension area to be reduced by half while managing manufacturing complexity through structured division of contact formation processes.
Solution Approach 2:
The patent implements a step structure for electrode pads in the extension area, utilizing vertical stacking to reduce the horizontal footprint. This dimensional approach allows the extension area to be minimized while maintaining necessary electrical connections through vertically arranged contacts.
3Area of stationary object
If contact separation layer is introduced to reduce extension area, then device complexity increases
Solution Approach 1:
The contact separation layer divides the extension area into distinct regions for lower and upper metal contacts, reducing the overall extension area by half. While this adds a structural layer, it enables more efficient space utilization and integration.
Solution Approach 2:
The contact separation layer acts as an intermediary structure between the substrate and the upper metal contacts. This intermediate layer facilitates the reduced extension area configuration by providing a structured interface for contact formation while managing the complexity of integrating multiple contact levels.
Data Source
AI summary
According to some embodiments of inventive concepts, vertical nonvolatile memory devices and related methods may reduce chip size. The nonvolatile memory device may include a substrate wherein a first direction is orthogonal with respect to a surface of the substrate and wherein the substrate includes a cell array area and an extension area. A first gate structure layer on the substrate may include a plurality of first gate layers. A contact separation layer may be on the first gate structure layer on the extension area. A second gate structure layer on the first gate structure layer and on the contact separation layer may include a plurality of second gate layers. A plurality of channel structures may extend in the first direction through the first and second gate structure layers on the cell array area. A plurality of first metal contacts may extend through the first gate structure layer in the first direction between the substate and the contact separation layer in the extension area. A plurality of second metal contacts may extend through the second gate structure layer in the first direction in the extension area. The contact separation layer may be between the first plurality of metal contacts and the second plurality of metal contacts, and each of the second metal contacts may be aligned with a respective one of the first metal contacts in the first direction. The device may also include a plurality of first electrode pads and a plurality of second electrode pads. Each of the first electrode pads may extend from a sidewall of a respective one of the first metal contacts to provide electrical coupling with a respective one of the first gate layers. Each of the second electrode pads may extend from a sidewall of a respective one of the second metal contacts to provide electrical coupling with a respective one of the second gate layers.