Vertical Memory Contacts for Dense Low-Loss Interconnects
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Solution Overview
Problem
Conventional 3D memory devices face challenges in efficiently coupling conductive lines to sense amplifiers due to traditional geometry, leading to increased interconnection area and parasitic current loss, which affects interconnection density and component count.
Innovation Solution
The implementation of vertical contacts in a tiered structure allows direct connection between conductive lines and circuitry components, eliminating the need for horizontal interconnections and reducing parasitic current loss by providing a more direct electrical path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional horizontal interconnection geometry is used to couple conductive lines to sense amplifiers, then the interconnection structure is simple to implement, but the interconnection area increases and parasitic current loss increases
Solution Approach 1:
The patent transitions from traditional horizontal interconnection geometry to a vertical interconnection structure. Conductive lines are coupled to sense amplifiers through vertical contacts that extend downward from the conductive lines to the sense amplifiers, utilizing the vertical dimension to reduce lateral interconnection area while maintaining electrical connectivity.
2Ease of manufacture
If traditional horizontal interconnection geometry is used to couple conductive lines to sense amplifiers, then the interconnection structure is simple to implement, but parasitic current loss increases
Solution Approach 1:
The patent transitions from traditional horizontal interconnection geometry to a vertical interconnection structure. Conductive lines are coupled to sense amplifiers through vertical contacts that extend downward from the conductive lines to the sense amplifiers, utilizing the vertical dimension to reduce lateral interconnection area while maintaining electrical connectivity.
3Productivity
If vertical contacts in tiered structure are used to directly connect conductive lines to circuitry components, then interconnection density increases and parasitic current loss reduces, but the device complexity increases
Solution Approach 1:
The patent implements vertical contacts that extend from conductive lines through multiple tiers to reach circuitry components in the substrate, utilizing the vertical dimension to achieve high interconnection density while systematically managing the increased structural complexity through organized tiered architecture.
Solution Approach 2:
The vertical contact structure serves multiple functions: it provides direct electrical connection between conductive lines and sense amplifiers, reduces parasitic current loss, increases interconnection density, and enables coupling to multiple tiers of circuitry components simultaneously, thereby justifying the increased device complexity through multiple performance benefits.
Data Source
AI summary
Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.