Vertical Memory Array Integration With Separate Control Logic
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Solution Overview
Problem
Conventional microelectronic device designs face challenges in reducing feature dimensions and separation distances while maintaining performance and simplifying fabrication, particularly in memory devices with vertical memory arrays, due to processing conditions affecting control logic devices and impeding size reduction and performance improvements.
Innovation Solution
A method of forming microelectronic devices that includes forming vertical memory arrays with sacrificial structures and insulative structures, along with control logic devices on a separate base structure, allowing for independent processing and integration with routing structures, thereby enabling compact and high-performance designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If control logic devices are integrated with memory array under the same processing conditions, then routing and interconnect structures can be formed, but processing conditions limit the configurations and performance of control logic devices
Solution Approach 1:
The patent divides the microelectronic device into two separate structures: a memory array structure and a control logic structure. This segmentation allows each structure to be processed independently under optimized conditions, eliminating the constraint where unified processing conditions limited control logic device performance while enabling routing and interconnect formation.
2Ease of manufacture
If conventional planar arrangements of transistors are used, then fabrication is simpler, but integration density and number of switching devices per unit area is reduced
Solution Approach 1:
The patent transitions from conventional two-dimensional planar transistor arrangements to a three-dimensional vertical memory array architecture. This dimensional change enables significantly higher integration density by stacking memory cells vertically, allowing more switching devices per unit area while maintaining manufacturability through standardized vertical processing techniques.
3Reliability
If quantities and dimensions of control logic devices are increased to improve performance, then memory cell ON/OFF speed and threshold switching voltage improve, but horizontal footprint of memory device increases
Solution Approach 1:
By implementing control logic devices on a separate base structure rather than integrating them within the horizontal plane of the memory array, the patent enables performance optimization without increasing the horizontal footprint. The vertical stacking architecture frees up horizontal space while allowing enhanced control logic configurations for improved memory cell switching performance.
4Productivity
If feature dimensions are reduced to increase integration density, then more features fit in unit area, but processing conditions become more constrained and fabrication difficulty increases
Solution Approach 1:
The patent segments the device into separately processable structures that can be fabricated independently and then integrated. This approach allows standard processing conditions to be used for each segment, avoiding the need to simultaneously satisfy conflicting processing requirements that arise when all features are miniaturized in a single integrated structure.
Data Source
AI summary
A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a preliminary stack structure comprising sacrificial structures and insulative structures vertically alternating with the sacrificial structures. A second microelectronic device structure comprising control logic circuitry is formed. The first microelectronic device structure is attached to the second microelectronic device structure to form an assembly. After forming the assembly, the sacrificial structures are at least partially replaced with conductive structures to form a stack structure. Contact structures are formed to extend through the stack structure. One or more of the contact structures are coupled to the control logic circuitry. Conductive line structures are formed over the stack structure. One or more of the conductive line structures are coupled to the one or more of the contact structures. Microelectronic devices, memory devices, and electronic systems are also described.