Vertical Transistor Memory Cells With Cup Capacitors for Higher Density
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to increased complexity and cost as feature sizes approach a lower limit, leading to density limitations and fabrication difficulties.
Innovation Solution
The introduction of vertical transistors with cup-shaped capacitors and low-leakage metal oxide semiconductor materials, along with a redesigned active area and fabrication method, allows for increased memory density and reduced cell size, utilizing cup-capacitors that can be formed before vertical transistors without mesh layers, and enabling high-temperature processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but fabrication complexity and cost increase as feature sizes approach a lower limit
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) vertical transistor architecture. The vertical transistor includes a channel extending in the vertical direction with source and drain regions positioned above and below the gate, enabling memory cells to utilize the vertical dimension for scaling. This dimensional change allows continued density improvement without the fabrication complexity penalties associated with scaling planar features to sub-10nm dimensions.
Solution Approach 2:
The patent employs metal oxide semiconductor materials (such as IGZO, IZO, GZO) with specific physical and chemical properties that enable low leakage current and compatibility with high-temperature processing. These material parameter changes allow the fabrication process to operate at temperatures of 400-450°C, simplifying the overall fabrication sequence and reducing process complexity compared to conventional scaled planar technologies.
2Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density is improved, but fabrication cost increases
Solution Approach 1:
By moving to 3D vertical transistors, the patent achieves higher memory density without requiring extremely small lateral feature sizes. This avoids the costly fabrication equipment and process steps needed for sub-10nm planar scaling, thereby reducing fabrication cost while maintaining density improvement.
Solution Approach 2:
The use of metal oxide semiconductor materials enables fabrication at moderate temperatures (400-450°C) using standard semiconductor processing equipment. This eliminates the need for expensive specialized processes required in advanced planar node fabrication, reducing both capital equipment costs and manufacturing complexity.
3Quantity of substance
If feature sizes of memory cells approach a lower limit, then memory density approaches an upper limit, but planar process and fabrication techniques become challenging
Solution Approach 1:
The vertical transistor architecture replaces lateral feature scaling with vertical stacking. Instead of reducing lateral dimensions to sub-10nm with corresponding precision requirements, the channel length is extended in the vertical direction with source/drain regions positioned above and below the gate, achieving density improvement through vertical integration rather than lateral miniaturization.
4Object-generated harmful factors
If vertical transistors with metal oxide semiconductor are used, then leakage performance is improved, but process temperature requirements increase
Solution Approach 1:
The patent utilizes metal oxide semiconductor materials (IGZO, IZO, GZO) that inherently provide low leakage current due to their wide bandgap properties. These materials enable fabrication at temperatures of 400-450°C, which is moderate compared to conventional scaled technologies. The material parameters are specifically selected to achieve both low leakage and process temperature compatibility.
Data Source
AI summary
Semiconductor devices and fabricating methods thereof are provided. The semiconductor device includes vertical transistors each including a semiconductor layer and a gate structure coupled to the semiconductor layer and cup-shaped capacitors coupled with the vertical transistors correspondingly. The semiconductor layer of each vertical transistor includes a vertical portion extending in a vertical direction and a lateral portion extending from a first end of the vertical portion in a lateral direction. The first lateral portions of the semiconductor layers of two adjacent vertical transistors in the lateral direction are connected with each other.