Vertical Memory Transistor Layout for Higher Density Arrays
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Solution Overview
Problem
Conventional planar memory cells face challenges in increasing memory density due to limitations in scaling down device dimensions, leading to high fabrication costs and complexity.
Innovation Solution
The use of vertical transistors with a semiconductor body extending in a first direction, including a doped source, drain, and channel portion, along with a storage unit and bit line arrangement that reduces the transistor area and simplifies interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes to increase memory density, then memory density improves, but fabrication complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to vertical (3D) memory cell architecture. The vertical transistor structure extends the channel in the vertical direction rather than laterally, enabling memory density improvement without proportionally increasing fabrication complexity. This dimensional change allows stacking multiple storage units vertically while maintaining manageable process complexity.
Solution Approach 2:
The memory cell is segmented into distinct vertical components: vertical transistor, storage unit, and bit line structure. This segmentation allows independent optimization of each component and simplifies the overall fabrication process by breaking down the complex planar structure into manageable vertical modules that can be formed through standardized deposition and etching steps.
2Quantity of substance
If planar process techniques are used to scale memory cells, then memory density improves, but manufacturing cost increases
Solution Approach 1:
By moving to vertical transistor and storage unit structures, the patent achieves memory density improvement through the third dimension (vertical stacking) rather than continuous lateral scaling. This approach uses standard semiconductor deposition and etching processes applied in vertical configurations, avoiding the need for increasingly complex planar lithography and processing required by traditional scaling methods.
3Productivity
If vertical transistors with staggered layout are used, then memory cell array efficiency improves, but device structure complexity increases
Solution Approach 1:
The staggered layout is achieved through vertical offset positioning of the bit line relative to the vertical transistor channel, rather than lateral staggering. This vertical bit line configuration, where the bit line is positioned at a different vertical level than the channel, enables efficient memory cell array packing while maintaining relatively simple individual device structures formed through sequential deposition and patterning steps.
Data Source
AI summary
In certain aspects, a memory device includes a vertical transistor, a storage unit, and a bit line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and in contact with a second terminal. The second terminal is another one of the source and the drain that is formed on all sides of a protrusion of the semiconductor body. The bit line is separated from the channel portion of the semiconductor body by the second terminal.