Vertical Memory Cell Layout for Higher Density and Lower Leakage
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling down due to increased complexity and cost as feature sizes approach limits, with limitations in memory density and fabrication complexity, particularly due to the lateral arrangement of transistors and interconnect structures.
Innovation Solution
The adoption of vertical transistors with a semiconductor body extending in a first direction and a gate structure coupled to at least one side, allowing for a more compact layout and simplified interconnects, along with the use of multi-gate transistors to reduce leakage current and improve channel control, and the bonding of memory arrays and peripheral circuits on different substrates to enhance efficiency and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology and circuit design, then memory density is improved, but fabrication complexity and cost increase significantly as feature sizes approach lower limits
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) stacked architecture. Memory cells are arranged in multiple tiers stacked vertically, with each tier containing transistors and storage units. This vertical stacking enables significantly higher memory density within the same footprint area, effectively moving the problem from lateral scaling limits to vertical integration, thereby avoiding the fabrication complexity associated with extreme lateral feature size reduction
2Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density is improved, but the area occupied by transistors and interconnect structures increases relative to the memory storage area
Solution Approach 1:
By stacking memory tiers vertically, the patent separates the transistor layer from the storage unit layer in the vertical dimension. Transistors in each tier control storage units in the same tier, allowing bit lines to be routed through vertical vias to contact storage units directly beneath or above the transistor. This arrangement minimizes the lateral area occupied by interconnect structures while maximizing the effective storage area, thereby improving the ratio of storage area to transistor area and increasing overall memory density
3Quantity of substance
If three-dimensional memory architecture is adopted to address density limitations, then memory density is improved, but device structure and interconnect routing become more complex
Solution Approach 1:
The patent divides the memory device into multiple discrete tiers, with each tier containing a complete set of transistors and storage units. This segmentation allows for modular fabrication and simplifies the overall device structure by repeating identical or similar unit cells vertically. Each tier can be independently formed using sequential deposition and etching processes, making the complex 3D structure manageable through systematic repetition of standardized building blocks
Solution Approach 2:
The patent forms alternating layers of transistor materials and storage unit materials in a predetermined sequence before final patterning and connection. This preliminary layering establishes the vertical stack architecture early in the fabrication process, enabling subsequent steps to focus on creating precise contacts and interconnects rather than building the entire 3D structure from scratch. The preliminary formation of material layers simplifies the overall device structure by pre-organizing components in their final vertical positions
Data Source
AI summary
A memory device includes a memory array and a peripheral circuit coupled to the memory array. The memory array includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The vertical transistor is disposed between the bit line and the storage unit along the first direction.