Vertical Transistor Memory Stack for Higher Density Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Planar memory cells face challenges in scaling due to limitations in feature size, leading to increased fabrication complexity and reduced memory density, which can be addressed by adopting a 3D memory architecture with vertical transistors and stacked storage units.
Innovation Solution
The implementation of a 3D memory device with vertical transistors, where a semiconductor body extends vertically, and stacked storage units, with interleaved dielectric and conductive layers, allows for increased memory density and reduced fabrication complexity. Additionally, the use of a staggered layout for memory cells and multiple stacked storage units further enhances cell density and reduces unit cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density increases, but fabrication complexity increases and feature size approaches lower limit
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) architecture by stacking multiple memory cell layers vertically. Each memory cell layer includes vertical transistors with semiconductor bodies extending in the vertical direction, allowing memory density to increase without further reducing lateral feature sizes, thereby avoiding the fabrication complexity and physical limits associated with continued planar scaling
2Quantity of substance
If feature sizes of memory cells are reduced, then memory density increases, but process and fabrication techniques become challenging and costly
Solution Approach 1:
By adopting vertical transistors where the semiconductor body extends in the vertical direction rather than laterally, the patent enables memory density improvement through increased stacking height rather than reduced feature size. This maintains larger, more manufacturable lateral dimensions while achieving high density through the third dimension
Solution Approach 2:
The memory device is divided into multiple discrete memory cell layers stacked vertically, with each layer containing vertical transistors and storage units. This segmentation allows standardized fabrication processes to be repeated for each layer, improving manufacturability compared to continuous planar scaling
3Quantity of substance
If 3D memory architecture is adopted with vertical transistors, then memory density increases, but device structure becomes more complex
Solution Approach 1:
The patent merges multiple functional components into integrated vertical structures: the vertical transistor channel, gate electrodes, and storage units are combined in a stacked configuration where the semiconductor body extends vertically and is surrounded by gate structures, with storage units positioned at specific locations along the vertical channel. This integration reduces the number of separate components and simplifies the overall device structure despite the three-dimensional architecture
Solution Approach 2:
The vertical transistor structure serves multiple functions: the semiconductor body provides the transistor channel, the surrounding gate electrodes provide control and electrical connection, and the stacked configuration provides both transistor functionality and storage unit integration. This multi-functionality reduces structural complexity by eliminating the need for separate planar transistor and capacitor structures
Data Source
AI summary
In certain aspects, a memory device includes a vertical transistor including a semiconductor body extending in a first direction, a stack structure including interleaved dielectric layers and conductive layers each extending perpendicularly to the first direction, an electrode layer including a conductive material and coupled to a first end of the semiconductor body, and a storage layer over the electrode layer. The electrode layer and the storage layer extend in the first direction through the stack structure.