Vertical Memory Device Architecture for Space Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing degree of integration and operating speed of memory devices lead to insufficient space for the peripheral circuit due to the growing occupation areas of the row decoder and page buffer circuits, limiting the integration and capacity of memory devices.
Innovation Solution
A vertical type memory device architecture is proposed, where the row control circuit, column control circuit, and peripheral circuit are stacked on a cell wafer, with the row decoder and page buffer circuit configured to extend in the direction of word lines and bit lines respectively, and the peripheral circuit is placed on a separate substrate to optimize space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the row decoder and page buffer circuits are expanded to increase integration, then the memory device capacity increases, but the occupation area of peripheral circuits increases, leaving insufficient space for the memory cell array
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked architecture. The row decoder, page buffer, and memory cell array are arranged in different vertical layers rather than competing for the same horizontal space. This dimensional change allows all components to coexist without the peripheral circuits occupying excessive area that would reduce memory capacity.
2Device complexity
If the peripheral circuits are placed in the same plane as the memory cell array, then the device complexity is reduced, but the signal delay increases due to longer signal paths
Solution Approach 1:
By stacking the row decoder and page buffer in vertical layers adjacent to or overlapping with the memory cell array, the signal path length is dramatically reduced. The three-dimensional arrangement allows direct vertical and lateral connections between components, eliminating the need for long horizontal signal paths that would increase delay.
Solution Approach 2:
The patent implements a nested arrangement where the row decoder and page buffer are positioned in overlapping or adjacent vertical regions with the memory cell array. This nesting allows components to share vertical space and minimizes the distance between interconnected elements, reducing signal propagation delay.
Data Source
AI summary
A memory device includes a cell wafer including a memory cell array; and a peripheral wafer including a row control circuit, a column control circuit and a peripheral circuit which control the memory cell array, and stacked on and bonded to the cell wafer in a first direction. The peripheral wafer includes a first substrate having a first surface and a second surface which face away from each other in the first direction; a first logic structure disposed on the first surface of the first substrate, and including the row control circuit and the column control circuit; and a second logic structure disposed on the second surface of the first substrate, and including the peripheral circuit.