Vertical Memory Stack Layout to Prevent Substrate Dishing
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Solution Overview
Problem
The increasing number of memory cell stacks in vertical memory devices complicates the manufacturing process, leading to decreased electrical reliability of integrated circuit devices.
Innovation Solution
The integration of a dummy stack structure at the same vertical level as the cell stack structures in the peripheral circuit region, which includes alternately stacked dummy insulating and support layers, helps in maintaining the planarity of the substrate and preventing dishing during the filling of channel holes, thereby enhancing the electrical reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cell stacks is increased to achieve large capacity and high integration, then the memory capacity is improved, but the manufacturing process complexity increases and electrical reliability decreases
Solution Approach 1:
A dummy stack structure is introduced as an intermediary element in the peripheral circuit region. This dummy stack includes dummy insulating layers and dummy support layers that mimic the structure of real cell stacks, serving as a structural placeholder to maintain substrate planarity and prevent dishing during manufacturing processes, thereby enabling higher stack counts while preserving electrical reliability
Solution Approach 2:
The dummy stack structure is selectively placed in the peripheral circuit region rather than uniformly across the entire substrate. This localized approach provides structural support where needed to prevent dishing during channel hole filling, while allowing the cell region to maintain its functional integrity for high-density memory storage
2Quantity of substance
If the number of memory cell stacks is increased, then the memory capacity is improved, but the manufacturing process difficulty increases
Solution Approach 1:
The dummy stack structure acts as a manufacturing aid by providing a structural reference during the channel hole filling process. It prevents substrate dishing that would otherwise occur when filling channel holes in high-density stack configurations, thereby simplifying the manufacturing process and improving yield without limiting the number of functional memory stacks
Solution Approach 2:
The dummy stack structure is formed in advance during the manufacturing process, before the final memory stacks are completed. This preliminary structural support is in place during critical processing steps such as channel hole filling, preventing dishing and ensuring manufacturing feasibility for high-capacity devices
3Quantity of substance
If the number of memory cell stacks is increased, then the memory capacity is improved, but the substrate planarity deteriorates due to dishing
Solution Approach 1:
The dummy stack structure serves as a structural intermediary that maintains substrate planarity during the manufacturing process. By providing a placeholder structure in the peripheral circuit region, it prevents the substrate from dishing when channel holes are filled in the cell region, thereby preserving the flatness required for high-density stack integration
Solution Approach 2:
The dummy stack structure acts as a counterweight to the structural stress caused by filling channel holes in the cell region. This dummy structure provides opposing structural support that prevents dishing and maintains substrate planarity, enabling the integration of a higher number of memory stacks
Data Source
AI summary
An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.