3D Vertical Memory Stack With Dummy Channel Thickness Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity, particularly in electronic systems requiring high-capacity data storage, and existing three-dimensional memory cell arrangements have not been optimized for efficient data storage solutions.
Innovation Solution
A semiconductor device is designed with a stack structure featuring alternately stacked interlayer insulating layers and gate electrodes, incorporating vertical memory and dummy structures with specific layer configurations and separation patterns to enhance data storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then data storage capacity is improved, but device complexity increases
Solution Approach 1:
The device is segmented into multiple functional layers including stack structures with alternating interlayer insulating layers and gate electrodes, vertical memory structures, vertical dummy structures, and separation patterns. This segmentation allows complex 3D functionality to be organized into manageable, repetitive modular units that can be manufactured using standardized processes.
Solution Approach 2:
The patent transitions from traditional 2D memory cell arrangements to 3D vertical stacking, where memory structures extend in the vertical direction perpendicular to the substrate. This dimensional change enables significantly increased storage capacity by utilizing the vertical space above the substrate rather than only horizontal plane area.
2Quantity of substance
If vertical memory and dummy structures are implemented with specific layer configurations, then data storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The stack structures, vertical memory structures, and vertical dummy structures are formed simultaneously in a preliminary fabrication step before subsequent separation. This preliminary action ensures that all vertical structures have consistent dimensions and layer configurations, reducing variability and simplifying subsequent manufacturing steps.
Solution Approach 2:
The patent specifies particular parameter relationships, such as the upper separation pattern penetrating through a specific number of gate electrodes (e.g., three upper gate electrodes) and the vertical structures extending to specific height levels. These parameter changes provide clear manufacturing targets that simplify process control while achieving the desired 3D architecture.
3Productivity
If upper separation patterns penetrate through multiple gate electrodes, then data storage efficiency is improved, but device complexity increases
Solution Approach 1:
The upper separation pattern is segmented into a first portion intersecting the vertical dummy structure and a second portion extending from the first portion and penetrating through the stack structure. This segmentation allows the separation pattern to efficiently divide and isolate memory structures while maintaining a systematic fabrication approach.
Solution Approach 2:
The upper separation pattern serves multiple functions simultaneously: it separates adjacent vertical memory structures, intersects with vertical dummy structures to define boundaries, and penetrates through gate electrodes to establish electrical isolation. This multi-functionality improves storage efficiency by enabling denser packing while managing complexity through a single integrated structure.
Data Source
AI summary
A semiconductor device and a data storage system including the same, the semiconductor device including a substrate structure; a stack structure; a vertical memory structure; a vertical dummy structure; and an upper separation pattern, wherein hen viewed on a plane at a first height level, higher than a height level of a lowermost end of the upper separation pattern, the dummy channel layer includes a first dummy channel region facing the dummy data storage layer and a second dummy channel region facing the dummy data storage layer, the first dummy channel region having a thickness different from a thickness of the second dummy channel region.