Vertical Memory Devices With Dummy Channels For Channel Isolation

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Solution Overview

Problem

In the manufacturing of vertical NAND flash memory devices, as the number of gate electrodes increases, the mold layer is divided into lower and upper mold layers, leading to challenges in forming channels and charge storage structures without connecting neighboring channel holes, which affects the performance and efficiency of the memory devices.

Innovation Solution

The implementation of a gate electrode structure with dummy channels and charge storage structures that have a narrower lower surface than the upper surface, along with a division pattern and contact plugs, allows for improved channel formation and connection, enhancing the performance characteristics of vertical memory devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the mold layer is divided into lower and upper mold layers to accommodate increased gate electrodes, then the number of gate electrodes can be increased, but neighboring channel holes become connected which degrades device performance

Engineering Contradiction:
Improvenumber of gate electrodesVSAvoidchannel isolation
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The mold layer is divided into lower and upper mold layers, and the division pattern is segmented to include dummy channels that physically separate neighboring channel holes. This segmentation prevents unwanted electrical connection while allowing increased gate electrode density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Dummy channels act as intermediary structures between neighboring channel holes. These dummy channels include dummy charge storage structures that serve as electrical barriers, preventing direct connection between adjacent channels while maintaining structural integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If dummy channels and dummy charge storage structures are added to prevent channel connection, then channel isolation is improved, but device structure becomes more complex

Engineering Contradiction:
Improvechannel isolationVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dummy channels and dummy charge storage structures are merged with the existing division pattern and charge storage structure formation processes. By combining these isolation features with standard manufacturing steps, the additional structural elements do not significantly increase overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The division pattern serves multiple functions: it provides mechanical support, defines channel boundaries, and includes dummy channels that provide electrical isolation. This multi-functionality reduces the need for separate dedicated isolation structures, thereby limiting complexity increase.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Quantity of substance

If channels are formed through divided mold layers, then more gate electrodes can be stacked, but manufacturing precision is required to prevent channel hole connection

Engineering Contradiction:
Improvenumber of gate electrodesVSAvoidchannel hole alignment
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

Dummy channels are formed in advance during the mold layer division process, creating pre-established isolation barriers. This preliminary action ensures that even with manufacturing variations, neighboring channel holes remain separated by the dummy channel structures.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dummy channels extend through the entire depth of the mold layers, effectively skipping over the critical interface region where lower and upper channels could connect. This through-depth isolation eliminates the need for precise alignment at the mold layer interface.

Inventive Principle:
Principle #21Skipping (Rushing through)

Data Source

PatentUS11672119B2Vertical memory devices
Publication Date: 2023.06.06 SAMSUNG ELECTRONICS CO LTD
  • US11672119B2 patent drawing
  • US11672119B2 patent drawing
  • US11672119B2 patent drawing

AI summary

A vertical memory device includes a gate electrode structure, channels, a charge storage structure, and a division pattern. The gate electrode includes gate electrodes spaced apart from each other in a first direction. The channel extends through the gate electrode structure, and includes a first portion and a second portion on and contacting the first portion. The second portion includes a lower surface having a width less than that of an upper surface of the first portion. The charge storage structure covers an outer sidewall of the channel. The division pattern extends between the channels in a second direction, and includes a first dummy channel and a first dummy charge storage structure covering a sidewall and a lower surface thereof. The first dummy channel includes the same material as that the channel, and the first dummy charge storage structure includes the same material as the charge storage structure.