Vertical Memory Stack Layout With Dummy Layers for CMP Reliability
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Solution Overview
Problem
The increasing number of memory cell stacks in vertical memory devices complicates the manufacturing process, leading to decreased electrical reliability of integrated circuit devices.
Innovation Solution
The integration of a dummy stack structure at the same vertical level as the cell stack structures in the peripheral circuit region, which includes alternately stacked dummy insulating and support layers, helps in maintaining the structural integrity and reliability by preventing dishing during the planarization process and ensuring accurate alignment of channel holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cell stacks is increased to achieve high integration and large capacity, then the memory capacity per chip is improved, but the manufacturing process complexity increases and electrical reliability decreases
Solution Approach 1:
The patent introduces dummy stack structures that replicate the form and stacking sequence of real memory cell stacks (alternating insulating layers and support layers) but without functional memory cells. These dummy stacks serve as structural copies that maintain process consistency during manufacturing, thereby preserving electrical reliability while enabling increased memory capacity through additional real stacks.
Solution Approach 2:
The dummy stack structures are positioned at the same vertical level as the memory cell stacks to preemptively compensate for structural instability and dishing issues that would arise from having too many stacked memory cells. This prior cushioning approach prevents manufacturing defects before they occur, maintaining reliability as the number of memory stacks increases.
2Quantity of substance
If the number of memory cell stacks is increased, then the component density per chip is improved, but the manufacturing process difficulty increases
Solution Approach 1:
By creating dummy stack structures that mirror the stacking sequence and physical dimensions of real memory cell stacks, the patent provides reference structures that simplify the manufacturing process. These copies enable consistent application of deposition and planarization processes across the entire wafer, reducing process difficulty even as component density increases.
Solution Approach 2:
The dummy stack structures are designed with the same alternating layer composition (insulating layers and support layers) as the memory cell stacks, creating structural homogeneity across the substrate. This uniformity ensures that manufacturing processes such as chemical vapor deposition and planarization proceed consistently across all regions, easing manufacturing complexity.
3Temperature
If the number of stacked memory cells is increased, then the vertical integration is improved, but the structural integrity deteriorates due to dishing during planarization
Solution Approach 1:
The dummy stack structures serve as structural replicas of the memory cell stacks, providing reference points that maintain uniform stress distribution during planarization. By copying the alternating layer structure (insulating layers and support layers), these dummy stacks prevent localized dishing that would compromise structural integrity in high vertical integration scenarios.
Solution Approach 2:
The dummy stack structures act as counterbalancing elements during the planarization process. By being positioned at the same vertical level as the memory cell stacks and having matching structural properties, they provide counterweight that prevents excessive removal of material during chemical mechanical polishing, thereby preserving structural integrity.
4Quantity of substance
If the number of memory cell stacks is increased, then the memory capacity is improved, but the alignment precision of channel holes deteriorates
Solution Approach 1:
The dummy stack structures replicate the vertical stacking sequence and lateral dimensions of memory cell stacks, serving as alignment reference structures. During multi-step manufacturing processes, these copied structures provide consistent registration targets that maintain alignment precision even when the number of memory cell stacks is increased for higher capacity.
Data Source
AI summary
An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.