Vertical Memory Devices With Dummy Through Via Contacts

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Solution Overview

Problem

Vertical memory devices with a cell over peripheral (COP) structure face issues with wiring defects due to the complexity of through via contacts, which can lead to electrical connectivity problems and device failures.

Innovation Solution

Incorporating dummy through via contacts adjacent to the through via contacts, these dummy contacts are electrically insulated from the lower transistor and help reduce defects by providing a structural support that maintains the aspect ratio of the through via contacts within a specific range, thereby enhancing the reliability of the electrical connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If through via contacts are used to connect peripheral circuit wiring to upper layers, then electrical connectivity is achieved, but wiring defects increase due to the complexity and aspect ratio constraints

Engineering Contradiction:
Improveelectrical connectivityVSAvoidwiring defects
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

Dummy through via contacts are formed adjacent to the actual through via contacts before final wiring is completed. These dummy contacts serve as preliminary structural supports that maintain the aspect ratio and provide mechanical stability during subsequent manufacturing processes, preventing defects in the actual through via contacts.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dummy through via contacts act as intermediary structures that do not directly participate in electrical connectivity but provide mechanical support and maintain geometric constraints. They serve as a mediator between the manufacturing process requirements and the final electrical connection reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If the aspect ratio of through via contacts is not controlled, then manufacturing is simpler, but electrical connectivity and reliability deteriorate

Engineering Contradiction:
Improvethrough via contact formationVSAvoidelectrical connectivity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The aspect ratio of through via contacts is controlled by introducing dummy through via contacts with specific dimensional parameters. The dummy contacts are positioned and sized to maintain the aspect ratio within the range of 5:1 to 15:1, ensuring reliable electrical connectivity while managing manufacturing complexity.

Inventive Principle:
Principle #35Parameter changes

3Object-affected harmful factors

If dummy through via contacts are added adjacent to through via contacts, then wiring defects are reduced, but device complexity increases

Engineering Contradiction:
Improvewiring defectsVSAvoidcontact structure
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

Dummy through via contacts are created as simplified copies of the actual through via contacts. They replicate the structural form and dimensional characteristics but are electrically isolated, providing the necessary mechanical support without adding complex electrical connection requirements.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS11456335B2Vertical memory devices
Publication Date: 2022.09.27 SAMSUNG ELECTRONICS CO LTD
  • US11456335B2 patent drawing
  • US11456335B2 patent drawing
  • US11456335B2 patent drawing

AI summary

A vertical memory device includes circuit patterns of peripheral circuits on a substrate, the circuit patterns including a lower conductive pattern, cell stack structures over the circuit patterns and spaced apart in a first horizontal direction, wherein each of the cell stack structures includes gate electrodes spaced apart in a vertical direction, a first insulating interlayer covering the cell stack structures and a portion between the cell stack structures, a through via contact passing through the first insulating interlayer between the cell stack structures to contact an upper surface of the lower conductive pattern, at least one dummy through via contact passing through the first insulating interlayer between the cell stack structures and disposed adjacent to the through via contact, and upper wiring on the through via contact.