Vertical Memory Epitaxial Layer for Channel Disconnection
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Solution Overview
Problem
The challenge is to prevent disconnection phenomena in vertical memory devices and enhance the characteristics of transistors forming memory cell strings, particularly in increasing the degree of integration and memory capacity while maintaining reliable channel layer connections.
Innovation Solution
A vertical memory device design featuring a substrate with stacked gate electrode layers, a channel layer penetrating through these layers, and a first epitaxial layer in contact with the channel layer, along with a gate dielectric layer with a sidewall portion and a lower surface portion, which helps prevent disconnection by filling through holes and reducing channel layer thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel layer thickness is reduced to increase integration density, then the degree of integration is improved, but the channel layer becomes prone to disconnection
Solution Approach 1:
An epitaxial layer is introduced as an intermediary component between the channel layer and the substrate. This epitaxial layer serves as a mediator that provides mechanical support and electrical connection to the thin channel layer, preventing disconnection while allowing the channel layer to maintain reduced thickness for high integration density.
Solution Approach 2:
The device employs a composite structure combining the channel layer with the epitaxial layer. This composite material approach allows the thin channel layer to function effectively for high-density integration while the epitaxial layer provides the necessary structural integrity and connection stability to prevent disconnection.
2Productivity
If the degree of integration is increased by stacking memory cells vertically, then the memory capacity is improved, but the complexity of maintaining channel layer integrity increases
Solution Approach 1:
The vertical memory structure is segmented into distinct functional layers: the channel layer for transistor operation and the epitaxial layer for structural support and connection. This segmentation allows each layer to be optimized independently, simplifying the maintenance of channel layer integrity in high-density vertical stacking configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents channel layer disconnection and enhances memory device integration and capacity by ensuring stable transistor performance and reduced channel layer thickness.
Implementation Method 1
growing a first epitaxial layer filling at least a portion of the through hole
Data Source
AI summary
A vertical memory device and method of manufacture thereof are provided. The vertical memory device includes gate electrode layers stacked on a substrate; a channel layer penetrating through the gate electrode layers; and a first epitaxial layer in contact with a lower portion of the channel layer and including a region having a diameter smaller than an external diameter of the channel layer.