Vertical Nonvolatile Memory Erase Voltage Ramping
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Solution Overview
Problem
Existing nonvolatile memory devices face challenges in efficiently erasing vertically stacked memory cells without inadvertently programming ground and string selection transistors during the erase operation, leading to reliability issues.
Innovation Solution
A control circuit is implemented that generates a monotonically increasing erase voltage, ramped from a first to a higher second voltage level, and drives vertical channel regions concurrently with electrically floating ground and string selection lines, using a totem-pole arrangement of transistors and a ramping circuit to prevent inadvertent programming of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional erase voltage is applied to vertically stacked memory cells, then erasure operation can be performed, but ground and string selection transistors are inadvertently programmed leading to reliability issues
Solution Approach 1:
The patent applies dynamics by transitioning from a static erase voltage to a dynamically ramping voltage that increases monotonically from a first voltage level to a higher second voltage level during the erase time interval. This dynamic voltage adjustment allows the erase operation to progress without inadvertently programming the ground and string selection transistors, as the gradual voltage increase prevents the sudden voltage spikes that cause inadvertent programming.
Solution Approach 2:
The patent changes the voltage parameter from a constant level to a monotonically increasing ramping voltage. The erase voltage generator produces a voltage that continuously increases from a first voltage level to a higher second voltage level during the erase time interval, and this parameter change enables effective erasure while avoiding inadvertent programming of selection transistors.
2Productivity
If vertically stacked memory cells are erased using conventional methods, then memory cells can be erased, but the process is time-consuming and inefficient
Solution Approach 1:
The patent implements continuity of useful action by applying the ramping erase voltage continuously throughout the entire erase time interval. The monotonically increasing voltage is maintained without interruption from the first voltage level to the higher second voltage level, ensuring continuous and efficient erasure of all vertically stacked memory cells simultaneously, thereby reducing the overall erase time.
Solution Approach 2:
The patent segments the erase operation into distinct voltage levels (first voltage level to higher second voltage level) that are applied to different portions of the vertically stacked memory cells during the time interval. This segmentation allows simultaneous erasure of multiple memory cell layers through the controlled voltage ramping process.
Data Source
AI summary
Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. A control circuit is provided, which is configured to drive the vertical channel regions with an erase voltage that is ramped from a first voltage level to a higher second voltage level during an erase time interval. This ramping of the erase voltage promotes time efficient erasure of vertically stacked nonvolatile memory cells with reduced susceptibility to inadvertent programming of ground and string selection transistors (GST, SST).