Vertical Channel Memory Structure With Etch Stop Via Contact
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Solution Overview
Problem
The high cost of using Silicon-on-insulator (SOI) substrates in vertical channel memory devices hinders the integration and development of semiconductor devices, as they are expensive.
Innovation Solution
A semiconductor device design that utilizes a peripheral circuit pattern, bit line structure, channel, word line, capacitor, and etch stop pattern, where the etch stop layer serves as an end point for polishing without relying on SOI substrates, thereby reducing gate structure length distribution and enhancing electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Silicon-on-insulator (SOI) substrates are used in vertical channel memory devices, then the device performance and integration are improved, but the manufacturing cost increases significantly
Solution Approach 1:
The patent replaces expensive SOI substrates with standard silicon substrates that have an etch stop layer. The etch stop layer serves as a disposable sacrificial layer during the manufacturing process, particularly during chemical mechanical polishing (CMP), where it acts as an endpoint indicator. This approach eliminates the need for costly SOI substrates while maintaining the vertical channel structure and device performance.
Solution Approach 2:
The etch stop layer functions as an intermediary between the standard silicon substrate and the overlying structures. During CMP processing, the etch stop layer protects the substrate while providing a clear polishing endpoint, and during etching processes, it prevents damage to the substrate. This intermediary layer enables the use of cheaper standard silicon substrates in place of expensive SOI substrates.
2Reliability
If the gate structure length distribution is reduced, then the electrical characteristics are enhanced, but the manufacturing precision requirements increase
Solution Approach 1:
The etch stop layer is formed in advance before the gate structures are fabricated. This preliminary layer provides a uniform reference plane that enables precise control of gate structure dimensions during subsequent processing steps. The etch stop layer's uniform thickness and material properties facilitate consistent gate length formation across the wafer, reducing length distribution without requiring excessive manufacturing precision.
Solution Approach 2:
The etch stop layer automatically serves as a polishing endpoint indicator during CMP processes. When the etch stop layer is exposed during polishing, it provides a clear visual and tactile signal that the polishing should stop, ensuring uniform gate structure lengths without requiring complex real-time monitoring systems. This self-service mechanism simplifies the manufacturing process while maintaining high precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the integration and electrical performance of semiconductor devices by reducing reliance on expensive SOI substrates and optimizing gate structure length, leading to enhanced electrical characteristics.
Implementation Method 1
the etch stop layer serves as an end point for polishing without relying on SOI substrates
Data Source
AI summary
A semiconductor device includes a peripheral circuit pattern on a substrate including first and second regions, a bit line structure on the peripheral circuit pattern electrically connected to the peripheral circuit pattern on the first region of the substrate, a channel on and electrically connected to the bit line structure, a word line at a side of the channel, a capacitor on and electrically connected to the channel, a plate electrode on an upper surface and a sidewall of the capacitor, an etch stop pattern on the second region of the substrate, and a first through via on and electrically connected to the peripheral circuit pattern on the second region of the substrate. A lower surface of the etch stop pattern is coplanar with a lower surface of the channel, and the first through via extends through the etch stop pattern in a vertical direction, and contacts the plate electrode.