Vertical Non-Volatile Memory Channel Layout for Etch Uniformity
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Solution Overview
Problem
Existing non-volatile memory devices face challenges in achieving high integration density and reliability due to variations in channel hole sizes during the manufacturing process, particularly caused by the etch loading effect when forming vertical channel structures.
Innovation Solution
The introduction of dummy channel structures and recess regions in the substrate design, which includes alternately stacking insulating and conductive layers along channel structures, and forming non-functional channel contacts or dummy channel structures to maintain uniformity in channel hole sizes, thereby reducing variations and enhancing integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical channel structures are formed to increase integration density, then integration density is improved, but channel hole size variations occur due to etch loading effect
Solution Approach 1:
Dummy channel holes are formed in advance in the substrate before the actual channel holes. These dummy holes are positioned in regions where etch loading would otherwise cause size variations. By pre-forming these dummy structures, the etch process conditions are standardized across all channel hole regions, ensuring uniform channel hole sizes while maintaining high integration density through vertical stacking.
2Reliability
If channel hole sizes are made uniform to improve reliability, then manufacturing complexity increases due to additional dummy structures
Solution Approach 1:
Dummy channel holes are created as simplified copies of the actual channel hole structure. These dummy holes replicate the essential geometric features and material composition of functional channel holes, allowing them to serve as etch process templates. This copying approach ensures that the etch loading effect is uniformly distributed, producing consistent channel hole sizes and improving device reliability without requiring complex process modifications.
Data Source
AI summary
A vertical-type nonvolatile memory device is provided in which differences between the sizes of channel holes in which channel structures are formed are reduced. The vertical-type nonvolatile memory device includes a substrate having channel hole recess regions in a surface thereof. Channel structures vertically protrude from the surface of the substrate on ones of the channel hole recess regions, and memory cell stacks including insulating and conductive layers are alternately stacked along sidewalls of the channel structures. A common source line extends along the surface of the substrate on other ones of the channel hole recess regions in a word line recess region, which separates adjacent memory cell stacks. Related fabrication methods are also discussed.