Vertical Memory Transistor Layout to Reduce Floating Body Effects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Planar memory cells face challenges in increasing density due to limitations in fabrication techniques, leading to high fabrication complexity and reduced memory cell array efficiency, with vertical transistors offering a potential solution but facing issues like floating body effects and increased current consumption.
Innovation Solution
The implementation of vertical transistors with partially doped semiconductor bodies and staggered layouts in 3D memory devices, allowing for reduced transistor area, simplified interconnect structures, and increased bit line process margins, along with face-to-face bonding of semiconductor structures to form memory cell arrays and peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes to increase density, then memory density improves, but fabrication complexity increases and process techniques become challenging
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to vertical (3D) transistor architecture. The vertical transistor includes a semiconductor body extending vertically with source and drain regions at different heights, enabling memory cells to utilize the third dimension for scaling. This dimensional change allows continued density improvement without proportionally increasing fabrication complexity, as the vertical structure can be formed using stacked processing steps rather than lateral lithography scaling.
2Productivity
If vertical transistors are implemented to increase memory density, then memory cell array efficiency improves, but floating body effects and increased current consumption occur
Solution Approach 1:
The patent applies selective doping to different regions of the vertical transistor structure. The semiconductor body has a first doped region (source), a second doped region (drain), and an undoped or lightly-doped channel portion in between. This local differentiation of doping concentrations allows the channel to maintain proper electrical characteristics and reduce floating body effects while still benefiting from the vertical architecture's density advantages.
3Reliability
If vertical transistors with fully doped semiconductor bodies are used, then transistor switching performance improves, but floating body effects increase
Solution Approach 1:
The patent changes the doping parameter distribution along the vertical axis of the semiconductor body. Instead of uniform doping, the structure has heavily doped source and drain regions at the ends with a transition to undoped or lightly-doped channel material in the middle portion. This parameter gradient allows strong carrier injection at the contacts while maintaining proper channel depletion characteristics, eliminating floating body effects that would occur with full doping.
Data Source
AI summary
A memory device includes a vertical transistor including a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The memory device further includes a storage unit coupled to one of the source and the drain, a word line extending in a second direction perpendicular to the first direction, and a body line coupled to the channel portion of the semiconductor body. The word line is between the storage unit and the body line in the first direction.