Vertical Memory Gate Layout With Air Gaps for RC Delay Reduction
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Solution Overview
Problem
High integration density in semiconductor dies leads to reduced reliability due to increased capacitive coupling between conductive features, resulting in higher power consumption and RC delay.
Innovation Solution
A vertical memory structure is developed with air gaps between conductive features, formed by creating energy removable blocks and transforming them into air gaps through a heat treatment process, which separates gate electrodes and conductive lines, reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high integration density is implemented in semiconductor dies, then device functionality and capacity are improved, but capacitive coupling between conductive features increases leading to reduced reliability
Solution Approach 1:
Air gap structures are introduced as intermediary elements between adjacent conductive features (gate electrodes and conductive lines). These air gaps act as electrical insulators that reduce parasitic capacitance coupling while occupying minimal space, thereby maintaining high integration density while improving device reliability by reducing capacitive interference
Solution Approach 2:
The patent utilizes air gap structures that create porous or void spaces between conductive features. These air-filled spaces serve as effective dielectric barriers that reduce capacitive coupling between adjacent conductors, allowing high integration density to be achieved without compromising reliability from excessive capacitive interference
2Quantity of substance
If high integration density is implemented, then device capacity is improved, but power consumption increases due to increased capacitive coupling
Solution Approach 1:
Air gap structures serve as intermediary dielectric elements that reduce parasitic capacitance between conductive features. By minimizing capacitive coupling, the energy required for signal transitions and charging/discharging of parasitic capacitances is reduced, thereby lowering power consumption while maintaining high integration density
3Quantity of substance
If high integration density is implemented, then device functionality is improved, but RC delay increases reducing device performance
Solution Approach 1:
Air gap structures are positioned as intermediary elements between conductive features to reduce parasitic capacitance. By lowering the capacitive component of RC delay while maintaining compact layouts for high integration density, signal propagation delays are reduced and device performance is improved
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases power consumption and RC delay, improving device performance and increasing yield rates by effectively reducing capacitive coupling between conductive features.
Implementation Method 1
transforming them into air gaps through a heat treatment process
Data Source
AI summary
The present disclosure provides a method for preparing a vertical memory structure with air gaps. The method includes providing a substrate; forming an impurity layer at an upper portion of the substrate; forming a semiconductor stack including a lower semiconductor pattern structure filling a recess on the substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate; forming a plurality of gate electrodes surrounding a sidewall of the semiconductor stack, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction; and forming a plurality of air gap structures disposed at outer sides of the plurality of gate electrodes respectively.