Vertical Channel Memory Gate Oxide Doping for Leakage Control
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Solution Overview
Problem
The degree of integration in two-dimensional semiconductor memory devices is limited due to the high cost and complexity of miniaturizing patterns, necessitating the development of vertical channel transistors to enhance integration and performance.
Innovation Solution
The semiconductor memory device incorporates a vertical channel transistor structure with specific metal oxide films and gate configurations, including doped impurity elements and varying thicknesses of gate metal oxide films to improve electrical characteristics and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If two-dimensional planar semiconductor memory device structure is used, then manufacturing process is simpler, but degree of integration is limited
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional vertical channel transistor structure. The channel extends in the vertical direction (third dimension) rather than horizontally, allowing multiple channels to be stacked vertically within the same footprint area. This dimensional change enables significantly higher degree of integration without requiring more complex planar processing techniques.
2Quantity of substance
If pattern miniaturization is pursued to increase integration, then degree of integration improves, but manufacturing cost increases due to ultra-expensive apparatuses required
Solution Approach 1:
Instead of continuing to miniaturize patterns in the planar direction (which requires increasingly expensive lithography equipment), the patent employs vertical channel transistors that utilize the third dimension. This approach achieves higher integration density by stacking channels vertically rather than packing them horizontally, thereby avoiding the need for ultra-expensive pattern miniaturization apparatuses while still increasing the degree of integration.
3Quantity of substance
If vertical channel transistor structure is implemented, then degree of integration improves, but electrical characteristics may deteriorate due to increased leakage current
Solution Approach 1:
The patent applies different material compositions and doping concentrations to different regions of the gate metal oxide film. Specifically, the first gate metal oxide film has a higher doping concentration than the capping gate metal oxide film, creating localized electrical properties that optimize both integration and electrical performance. This local quality variation allows control of leakage current in the vertical channel while maintaining high integration density.
Solution Approach 2:
The patent modifies the doping concentration parameter of the gate metal oxide film to optimize electrical characteristics. By setting the doping concentration of the first gate metal oxide film higher than that of the capping gate metal oxide film, the invention controls the electrical properties of the vertical channel transistor, thereby reducing leakage current and improving reliability while maintaining the benefits of vertical channel structure for high integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical channel transistor structure enhances integration and reduces leakage current, improving the overall performance and reducing manufacturing costs.
Implementation Method 1
the first gate metal oxide film includes a doped impurity element
Data Source
AI summary
A semiconductor memory device includes a channel region, a word line extending in a first direction, a gate insulating film being between the channel region and the word line and including silicon oxide, a first gate metal oxide film being between the gate insulating film and the word line, the first gate metal oxide film including first metal oxide, and a capping gate metal oxide film on an upper face of the word line and including second metal oxide, wherein the first gate metal oxide film includes a doped impurity element, and a concentration of the doped impurity element in the first gate metal oxide film is greater than a concentration of the doped impurity element in the capping gate metal oxide film.