Vertical Memory Gate Electrode Fluorine Damage Prevention
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Solution Overview
Problem
Existing vertical memory devices face issues with damage to adjacent layers during the formation of gate electrodes due to fluorine gas, which can lead to defects and poor electrical characteristics.
Innovation Solution
A semiconductor device design featuring a conductive barrier pattern and a filling layer pattern, where the conductive barrier pattern is formed on the inner walls of vertical openings and the filling layer pattern is positioned between the gate electrode and the conductive barrier, reducing the path for fluorine gas and minimizing damage to adjacent layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate electrodes are formed by deposition process using fluorine-containing source gas, then gate electrode formation is achieved, but adjacent layers (oxide layer, ONO layer) are damaged by remaining fluorine gas
Solution Approach 1:
A filling layer pattern is introduced as an intermediary element between the gate electrode and the adjacent insulating layers. This filling layer acts as a barrier that prevents remaining fluorine gas from reaching and damaging the oxide layer or ONO layer during the deposition process, while still allowing the gate electrode to be properly formed
Solution Approach 2:
The structure is segmented by dividing the area near the gate electrode into distinct regions: the gate electrode itself, the filling layer pattern positioned between the gate electrode and adjacent layers, and the insulating layers. This segmentation isolates the harmful fluorine gas effects to a localized area
2Object-affected harmful factors
If conductive barrier pattern and filling layer pattern are added to prevent fluorine gas damage, then damage to adjacent layers is reduced, but device structure becomes more complex
Solution Approach 1:
The conductive barrier pattern and filling layer pattern are merged into a single integrated structure that serves both as a protective barrier against fluorine gas and as part of the gate electrode assembly. This combined structure reduces the need for separate protective layers while maintaining the protective function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents damage to adjacent layers, reducing defects and improving the electrical characteristics of the vertical memory devices by containing the fluorine gas and allowing for the effective formation of gate electrodes.
Implementation Method 1
A semiconductor device design featuring a conductive barrier pattern and a filling layer pattern, where the conductive barrier pattern is formed on the inner walls of vertical openings and the filling layer pattern is positioned between the gate electrode and the conductive barrier, reducing the path for fluorine gas and minimizing damage to adjacent layers
Data Source
AI summary
A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.