Vertical Memory Gate Electrode Formation for Mold Stability

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In the manufacturing of VNAND flash memory devices, the increasing aspect ratio of molds with multiple sacrificial layers leads to tilting issues during the formation of openings, affecting the integrity and stability of the vertical memory device structure.

Innovation Solution

The vertical memory device design includes a channel structure with gradually increasing width portions, gate electrodes surrounding the channel, and an insulating isolation pattern that contacts the gate electrodes, allowing for proper formation of gate electrodes before subsequent openings, thereby preventing tilting and enhancing structural stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of sacrificial layers is increased to improve integration, then the degree of integration is improved, but the aspect ratio of the mold increases causing tilting

Engineering Contradiction:
Improvedegree of integrationVSAvoidmold stability
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The gate electrode is formed in advance before the opening is formed through the mold. This preliminary formation of the gate electrode provides internal support structure that prevents mold tilting during subsequent processing steps, allowing the use of multiple sacrificial layers for higher integration without compromising mold stability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The mold structure is divided into multiple sacrificial layers stacked vertically. By segmenting the mold into discrete layers rather than using a single thick structure, the patent enables better distribution of mechanical stresses and facilitates the preliminary gate electrode formation between layers, resolving the stability issue while maintaining high integration

Inventive Principle:
Principle #1Segmentation

2Productivity

If the aspect ratio of the mold is increased by stacking more sacrificial layers, then the degree of integration is improved, but the mold tilts after opening formation

Engineering Contradiction:
Improvedegree of integrationVSAvoidmold alignment
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The gate electrode is formed preliminarily before opening formation to provide structural support that maintains mold alignment during high aspect ratio operations, ensuring manufacturing precision is preserved despite increased integration density

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The gate electrode acts as an intermediary structural element between the substrate and the overlying mold structure. This intermediary component provides mechanical reinforcement that prevents tilting and maintains alignment precision during the formation and processing of high aspect ratio molds with multiple sacrificial layers

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11430804B2Vertical memory devices
Publication Date: 2022.08.30 SAMSUNG ELECTRONICS CO LTD
  • US11430804B2 patent drawing
  • US11430804B2 patent drawing
  • US11430804B2 patent drawing

AI summary

A vertical memory device is provided. The vertical memory device includes gate electrodes formed on a substrate and spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, the gate electrodes including a first gate electrode and a second gate electrode that is interposed between the first gate electrode and the substrate; a channel extending through the gate electrodes in the first direction; an insulating isolation pattern extending through the first gate electrode in the first direction, and spaced apart from the first gate electrode in a second direction substantially parallel to the upper surface of the substrate; and a blocking pattern disposed on an upper surface, a lower surface and a sidewall of each of the gate electrodes, the sidewall of the gate electrodes facing the channel. The insulating isolation pattern directly contacts the first gate electrode.