Vertical Memory Gate Line Segmentation for Structural Reliability
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Solution Overview
Problem
As the degree of integration in vertical memory devices increases, the reliability of the stacked gate lines and insulation layers becomes a critical concern, requiring improved structural and mechanical reliability to maintain device performance.
Innovation Solution
A vertical memory device design featuring gate lines stacked with step portions, contact spacers formed from silicon nitride or silicon oxynitride, and a mold protection layer of silicon oxide, with selective contact spacer formation on specific contacts to enhance reliability and prevent damage during the photo process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the stacked number of gate lines and insulation layers is increased to achieve higher degree of integration, then device capacity increases, but structural and mechanical reliability deteriorates
Solution Approach 1:
The gate lines are segmented into multiple stacked layers (first gate line, second gate line, third gate line) with insulation layers between them. This segmentation allows the device to achieve higher integration capacity while maintaining structural reliability through distributed stress across multiple smaller components rather than a single large structure.
Solution Approach 2:
The gate lines and insulation layers are arranged in a nested vertical stack configuration, where each gate line is surrounded by insulation layers. This nesting approach maximizes the use of vertical space to increase the number of gate lines per unit area while maintaining mechanical stability through the protective insulation layers.
2Productivity
If more gate lines are stacked vertically, then integration density improves, but mechanical strength and resistance to damage during photo process deteriorate
Solution Approach 1:
The device employs composite material structures where gate lines (conductive material) are combined with insulation layers (dielectric material) in a stacked configuration. This composite approach provides both the electrical functionality of multiple gate lines and the mechanical protection needed to withstand photo process damage, as the insulation layers act as protective barriers.
Solution Approach 2:
The insulation layers are positioned beforehand between the gate lines to provide cushioning and protection against mechanical damage during the photo process. This prior cushioning prevents direct exposure of the fragile gate line structures to damaging forces, maintaining their integrity throughout manufacturing.
Data Source
AI summary
A vertical memory device includes a substrate, gate lines, channels, contacts and contact spacers. The gate lines are stacked on top of each other on the substrate. The gate lines are spaced apart from each other in a vertical direction with respect to a top surface of the substrate. The gate lines include step portions that extend in a parallel direction with respect to the top surface of the substrate. The channels extend through the gate lines in the vertical direction. The contacts are on the step portions of the gate lines. The contact spacers are selectively formed along sidewalls of a portion of the contacts.